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The XPP Architecture and Its Co-simulation Within the Simulink Environment

Field Programmable Logic and Application, 2004, p.761-770

2004

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Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques

Embedded Computer Systems: Architectures, Modeling, and Simulation, 2005, p.12-21

2005

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High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures

Journal of Integrated Circuits and Systems, 2020-11, Vol.1 (1), p.23-31

2020

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Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

Field Programmable Logic and Application, 2003, p.1111-1114

2003

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Functional modeling techniques for a wireless LAN OFDM transceiver

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3970-3973 Vol. 4

2005

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A linear model for high-level delay estimation in VDSM on-chip interconnects

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1078-1081 Vol. 2

2005

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Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems

Design automation for embedded systems, 2003-12, Vol.8 (4), p.297-308

2003

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Transition activity estimation for general correlated data distributions [IC power estimation]

16th International Conference on VLSI Design, 2003. Proceedings, 2003, p.440-445

2003

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On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2004, p.819-828

2004

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Limits for switching power consumption in encoded interconnects

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005, 2005, Vol.1, p.27-30 Vol. 1

2005

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Process variations aware robust on-chip bus architecture synthesis for MPSoCs

2008 IEEE International Symposium on Circuits and Systems, 2008, p.2989-2992

2008

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System design challenges in ubiquitous computing environments

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004, 2004, p.11-14

2004

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Consistency control in data-driven design automation environments

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005, 2005, Vol.2, p.629-632 Vol. 2

2005

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Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.169-180

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An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs

2008 Design, Automation and Test in Europe, 2008, p.698-703

2008

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A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.6 pp.

2006

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Accurate capture of timing parameters in inductively-coupled on-chip interconnects

Proceedings of the 17th symposium on Integrated circuits and system design, 2004, p.117-122

2004

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A stochastic framework for communication architecture evaluation in networks-on-chip

Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on, 2003, Vol.1, p.253-256 vol.1

2003

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Power estimation based on transition activity analysis with an architecture precise rapid prototyping system

Proceedings 13th IEEE International Workshop on Rapid System Prototyping, 2002, p.138-143

2002

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A general method for function synthesis

International journal of control, 1971-07, Vol.14 (1), p.197-200

MURGAN, A. T.

1971

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On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.242-254

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Power consumption in point-to-point interconnect architectures

Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 2002, p.155-160

2002

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Computation with chaos in discrete-time neuro-fuzzy networks

Neural network world, 1996-01, Vol.6 (4), p.553-562

1996

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An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs

Proceedings of the conference on Design, automation and test in Europe, 2008, p.698-703

2008

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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

2006 IFIP International Conference on Very Large Scale Integration, 2006, p.296-301

2006

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The XPP Architecture and Its Co-simulation Within the Simulink Environment

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques

High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

Functional modeling techniques for a wireless LAN OFDM transceiver

A linear model for high-level delay estimation in VDSM on-chip interconnects

Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems

Transition activity estimation for general correlated data distributions [IC power estimation]

On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects

Limits for switching power consumption in encoded interconnects

Process variations aware robust on-chip bus architecture synthesis for MPSoCs

System design challenges in ubiquitous computing environments

Consistency control in data-driven design automation environments

Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Accurate capture of timing parameters in inductively-coupled on-chip interconnects

A stochastic framework for communication architecture evaluation in networks-on-chip

Power estimation based on transition activity analysis with an architecture precise rapid prototyping system

A general method for function synthesis

On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects

Power consumption in point-to-point interconnect architectures

Computation with chaos in discrete-time neuro-fuzzy networks

An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs

Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

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