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Kinetic Velocity Model to Account for Ballistic Effects in the Drift-Diffusion Transport Approach
IEEE transactions on electron devices, 2017-11, Vol.64 (11), p.4599-4606
2017
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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond
IEEE electron device letters, 2017-12, Vol.38 (12), p.1657-1660
2017
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Extending drift-diffusion paradigm into the era of FinFETs and nanowires
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.242-245
2015
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Effectiveness of Stressors in Aggressively Scaled FinFETs
IEEE transactions on electron devices, 2012-06, Vol.59 (6), p.1592-1598
2012
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Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing
IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1350-1367
2006
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Diagnosis of Optical Lithography Faults With Product Test Sets
IEEE transactions on computer-aided design of integrated circuits and systems, 2008-09, Vol.27 (9), p.1657-1669
2008
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FinFET to nanowire transition at 5nm design rules
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.254-257
2015
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Intentional Distortion of Transistor Shape to Improve Circuit Performance
IEEE electron device letters, 2010-01, Vol.31 (1), p.62-64
2010
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A 3-D TCAD Framework for NBTI-Part I: Implementation Details and FinFET Channel Material Impact
IEEE transactions on electron devices, 2019-05, Vol.66 (5), p.2086-2092
2019
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A 3-D TCAD Framework for NBTI, Part-II: Impact of Mechanical Strain, Quantum Effects, and FinFET Dimension Scaling
IEEE transactions on electron devices, 2019-05, Vol.66 (5), p.2093-2099
2019
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Exploring Power Savings of Gate-All-Around Cryogenic Technology
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2
2023
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Modeling Performance and Thermal Induced Reliability Issues of a 3nm FinFET Logic Chip Operation in a Fan-Out and a Flip-Chip Packages
2019 18th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2019, p.107-112
2019
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FinFET/nanowire design for 5nm/3nm technology nodes: Channel cladding and introducing a "bottleneck" shape to remove performance bottleneck
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2017, p.67-69
2017
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Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models
Microelectronics and reliability, 2005-09, Vol.45 (9), p.1305-1310
2005
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Effectiveness of strained-Si technology for thin-body MOSFETs
2012 IEEE International SOI Conference (SOI), 2012, p.1-2
2012
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A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND
2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.9B.3-1-9B.3-6
2024
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On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, p.172-175
2018
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Exploring doping options and variability of trigate transistors using atomistic process and device simulations
Journal of vacuum science and technology. B, Nanotechnology & microelectronics, 2010-01, Vol.28 (1), p.C1-C1H4
2010
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Power-performance-area engineering of 5nm nanowire library cells
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.433-436
2015
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14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain
2012 International Silicon-Germanium Technology and Device Meeting (ISTDM), 2012, p.1-2
2012
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Modeling and optimization of group IV and III-V FinFETs and nano-wires
2014 IEEE International Electron Devices Meeting, 2014, p.7.4.1-7.4.4
2014
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Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
2012 International Electron Devices Meeting, 2012, p.18.3.1-18.3.4
2012
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High speed phase detector design
2003 46th Midwest Symposium on Circuits and Systems, 2003, Vol.1, p.213-216 Vol. 1
2003
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Modeling of deterministic within-die variation in timing analysis, leakage current analysis, and delay fault diagnosis
2007
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Modeling of deterministic within -die variation in timing analysis, leakage current analysis, and delay fault diagnosis
2007
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