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Ruthenium(II) Complexes of a Xanthene-Spanned Dicarbene Ligand

Inorganic chemistry, 2023-11, Vol.62 (46), p.18901-18914

2023

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Trace-driven memory simulation: a survey

ACM computing surveys, 1997-06, Vol.29 (2), p.128-170

1997

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An analytical model for designing memory hierarchies

IEEE transactions on computers, 1996-10, Vol.45 (10), p.1180-1194

1996

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The bi-mode branch predictor

Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, 1997, p.4-13

1997

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Using modern processing technology to improve signal to noise ratio, a perth basin 3D land case study

ASEG Extended Abstracts, 2009-12, Vol.2009 (1), p.1-8

2009

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Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques

ACM transactions on embedded computing systems, 2023-01, Vol.22 (2), p.1-3, Article 27

2023

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Multilevel optimization of pipelined caches

IEEE transactions on computers, 1997-10, Vol.46 (10), p.1093-1102

1997

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Analysis and design of latch-controlled synchronous digital circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-03, Vol.11 (3), p.322-333

1992

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Recognizing Partially Occluded Parts

IEEE transactions on pattern analysis and machine intelligence, 1985-07, Vol.PAMI-7 (4), p.410-421

1985

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Critical paths in circuits with level-sensitive latches

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.273-291

1995

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A semi-Markov model for the performance of multiple-bus systems

IEEE transactions on computers, 1985-10, Vol.C-34 (10), p.934-942

1985

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Analysis of branch prediction via data compression

ASPLOS VII 1995: Architectural Support for Programmimg Languages and Operating Systems, 1996, Vol.30 (5), p.128-137

1996

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Optimum focusing from filtered dense velocities picking

ASEG Extended Abstracts, 2003-08, Vol.2003 (2), p.1-4

2003

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Gallium-arsenide process evaluation based on a RISC microprocessor example

IEEE journal of solid-state circuits, 1993-10, Vol.28 (10), p.1030-1037

1993

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Synchronization of pipelines

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-08, Vol.12 (8), p.1132-1146, Article 1132

1993

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Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

Journal of signal processing systems, 2014-09, Vol.76 (3), p.225-234

2014

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Overview of complementary GaAs technology for high-speed VLSI circuits

IEEE transactions on very large scale integration (VLSI) systems, 1998-03, Vol.6 (1), p.47-51

1998

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Multiple Bus Architectures

Computer (Long Beach, Calif.), 1987-06, Vol.20 (6), p.42-48

1987

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Osteoarthritis [119-126]: 119. The Value of HFE Genotyping in Exceptional Osteoarthritis

Rheumatology (Oxford, England), 2010-04, Vol.49 (Supplement 1), p.i78-i80

2010

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Multilevel optimization in the design of a high-performance GaAs microcomputer

IEEE journal of solid-state circuits, 1991-05, Vol.26 (5), p.763-767

1991

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Translation and execution of distributed Ada programs: Is it still Ada?

IEEE transactions on software engineering, 1989-03, Vol.15 (3), p.281-292

1989

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A look at several memory management units, TLB-refill mechanisms, and page table organizations

Operating systems review, 1998-12, Vol.32 (5), p.295-306

1998

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Timing Issues in the Distributed Execution of Ada Programs

IEEE transactions on computers, 1987-04, Vol.C-36 (4), p.449-459

1987

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Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique

The International journal of robotics research, 1989-12, Vol.8 (6), p.110-131

1989

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Unifying Robot Arm Control

IEEE transactions on industry applications, 1984-11, Vol.IA-20 (6), p.1554-1563

1984

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Ruthenium(II) Complexes of a Xanthene-Spanned Dicarbene Ligand

Trace-driven memory simulation: a survey

An analytical model for designing memory hierarchies

The bi-mode branch predictor

Using modern processing technology to improve signal to noise ratio, a perth basin 3D land case study

Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques

Multilevel optimization of pipelined caches

Analysis and design of latch-controlled synchronous digital circuits

Recognizing Partially Occluded Parts

Critical paths in circuits with level-sensitive latches

A semi-Markov model for the performance of multiple-bus systems

Analysis of branch prediction via data compression

Optimum focusing from filtered dense velocities picking

Gallium-arsenide process evaluation based on a RISC microprocessor example

Synchronization of pipelines

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

Overview of complementary GaAs technology for high-speed VLSI circuits

Multiple Bus Architectures

Osteoarthritis [119-126]: 119. The Value of HFE Genotyping in Exceptional Osteoarthritis

Multilevel optimization in the design of a high-performance GaAs microcomputer

Translation and execution of distributed Ada programs: Is it still Ada?

A look at several memory management units, TLB-refill mechanisms, and page table organizations

Timing Issues in the Distributed Execution of Ada Programs

Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique

Unifying Robot Arm Control

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