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On-chip charge pump design for 3D non-volatile flash memory: from industry perspective

Integration (Amsterdam), 2024-01, Vol.94, p.102093, Article 102093

2024

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Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Integration (Amsterdam), 2017-09, Vol.59, p.64-74

2017

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Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs

Integration (Amsterdam), 2017-06, Vol.58, p.116-124

2017

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Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit

IET circuits, devices & systems, 2016-01, Vol.10 (1), p.44-53

2016

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Grouped through silicon vias for lower L d i /d t drop in three‐dimensional integrated circuit

IET circuits, devices & systems, 2016-01, Vol.10 (1), p.44-53

2016

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Investigation of reliability and security issues in through silicon via based three-dimensional integrated circuits

Mossa, Siraj Fulum

2016

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Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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Introducing redundant TSV with low inductance for 3-D IC

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014, p.117-120

2014

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On-chip charge pump design for 3D non-volatile flash memory: from industry perspective

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs

Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit

Grouped through silicon vias for lower L d i /d t drop in three‐dimensional integrated circuit

Investigation of reliability and security issues in through silicon via based three-dimensional integrated circuits

Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs

Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective

Introducing redundant TSV with low inductance for 3-D IC

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