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A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing

IEEE access, 2022, Vol.10, p.43003-43012

2022

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A shared synapse architecture for efficient FPGA implementation of autoencoders

PloS one, 2018-03, Vol.13 (3), p.e0194049-e0194049

2018

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A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation

Neural Information Processing, p.821-829

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Learning reservoir dynamics with temporal self-modulation

Communications physics, 2024-01, Vol.7 (1), p.29-11, Article 29

2024

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Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Neural Information Processing, p.240-247

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Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation

Artificial Neural Networks and Machine Learning – ICANN 2016, p.391-398

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An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

IEEE access, 2021-01, Vol.9, p.2644-2654

2021

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FPGA Implementation of Autoencoders Having Shared Synapse Architecture

Neural Information Processing, p.231-239

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Initial states and analog switching behaviors of two major tantalum oxide resistive memories

Japanese Journal of Applied Physics, 2020-04, Vol.59 (4), p.44004

2020

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A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines

Neural Information Processing, p.248-255

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An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots

IEEE access, 2020-01, Vol.8, p.212066-212078

2020

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Experimental distinction between chaotic and strange nonchaotic attractors on the basis of consistency

Chaos (Woodbury, N.Y.), 2013-06, Vol.23 (2), p.023110-023110

2013

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Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor

Journal of robotics and mechatronics, 2015-12, Vol.27 (6), p.691-697

2015

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Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-1

2018

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A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

IEEE transaction on neural networks and learning systems, 2023-01, Vol.34 (1), p.394-408

2023

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Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links

Journal of robotics, networking and artificial life, 2017, Vol.4 (1), p.91-96

2017

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Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

Neural Information Processing, p.17-24

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Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks

IEEE transactions on circuits and systems. II, Express briefs, 2022-09, Vol.69 (9), p.3640-3644

2022

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A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

IEEE journal of solid-state circuits, 2015-06, Vol.50 (6), p.1372-1381

2015

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A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors

Japanese Journal of Applied Physics, 2020-04, Vol.59 (4), p.40604

2020

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Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.2849-2852

2011

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A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection

IPSJ Online Transactions, 2012, Vol.5, pp.177-185

2012

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A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation

Circuits, systems, and signal processing, 2015-02, Vol.34 (2), p.605-623

2015

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A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.2152-2156

2022

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A hardware intelligent processing accelerator for domestic service robots

Advanced robotics, 2020-07, Vol.34 (14), p.947-957

2020

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A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing

A shared synapse architecture for efficient FPGA implementation of autoencoders

A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation

Learning reservoir dynamics with temporal self-modulation

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

FPGA Implementation of Autoencoders Having Shared Synapse Architecture

Initial states and analog switching behaviors of two major tantalum oxide resistive memories

A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines

An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots

Experimental distinction between chaotic and strange nonchaotic attractors on the basis of consistency

Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor

Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links

Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors

Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation

A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection

A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation

A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing

A hardware intelligent processing accelerator for domestic service robots

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