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An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.903-914

2017

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Energy-Efficiency and Accuracy of Stochastic Computing Circuits in Emerging Technologies

IEEE journal on emerging and selected topics in circuits and systems, 2014-12, Vol.4 (4), p.475-486

2014

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DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.237-242

2015

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Embedded Deep Learning: Algorithms, Architectures and Circuits for Always-On Neural Network Processing

1, 2018

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Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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An Always-On 3.8 \mu J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.158-172

2019

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14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.246-247

2017

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Energy-efficient ConvNets through approximate computing

2016 IEEE Winter Conference on Applications of Computer Vision (WACV), 2016, p.1-8

2016

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An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.222-224

2018

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BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, p.1-4

2018

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Minimum energy quantized neural networks

2017 51st Asilomar Conference on Signals, Systems, and Computers, 2017, p.1921-1925

2017

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Distilling Optimal Neural Networks: Rapid Search in Diverse Spaces

2021 IEEE/CVF International Conference on Computer Vision (ICCV), 2021, p.12209-12218

2021

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An Always-On 3.8 [Formula Omitted]J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.158

2019

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A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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Optimized Hierarchical Cascaded Processing

IEEE journal on emerging and selected topics in circuits and systems, 2018-12, Vol.8 (4), p.884-894

2018

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Embedded Deep Neural Network Processing: Algorithmic and Processor Techniques Bring Deep Learning to IoT and Edge Devices

IEEE solid state circuits magazine, 2017, Vol.9 (4), p.55-65

2017

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DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.488-493

2017

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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.212-214

2024

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TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs

Proceedings of the 55th Annual Design Automation Conference, 2018, p.1-10

2018

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Efficiently Combining SVD, Pruning, Clustering and Retraining for Enhanced Neural Network Compression

Proceedings of the 2nd International Workshop on Embedded and Mobile Deep Learning, 2018, p.1-6

2018

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Energy and accuracy in multi-stage stochastic computing

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014, p.197-200

2014

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Conclusions, Contributions, and Future Work

Embedded Deep Learning, 2018, p.195-200

2018

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Hardware-Algorithm Co-optimizations

Embedded Deep Learning, 2018, p.55-88

2018

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Circuit Techniques for Approximate Computing

Embedded Deep Learning, 2018, p.89-113

2018

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Optimized Hierarchical Cascaded Processing

Embedded Deep Learning, 2018, p.33-54

2018

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An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

Energy-Efficiency and Accuracy of Stochastic Computing Circuits in Emerging Technologies

DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing

Embedded Deep Learning: Algorithms, Architectures and Circuits for Always-On Neural Network Processing

Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor

An Always-On 3.8 \mu J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI

Energy-efficient ConvNets through approximate computing

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS

Minimum energy quantized neural networks

Distilling Optimal Neural Networks: Rapid Search in Diverse Spaces

An Always-On 3.8 [Formula Omitted]J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS

A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

Optimized Hierarchical Cascaded Processing

Embedded Deep Neural Network Processing: Algorithmic and Processor Techniques Bring Deep Learning to IoT and Edge Devices

DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs

Efficiently Combining SVD, Pruning, Clustering and Retraining for Enhanced Neural Network Compression

Energy and accuracy in multi-stage stochastic computing

Conclusions, Contributions, and Future Work

Hardware-Algorithm Co-optimizations

Circuit Techniques for Approximate Computing

Optimized Hierarchical Cascaded Processing

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