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Automated bus generation for multiprocessor SoC design
IEEE transactions on computer-aided design of integrated circuits and systems, 2004-11, Vol.23 (11), p.1531-1549
2004
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A Novel Parallel Banker's Algorithm for System-on-a-Chip
IEEE transactions on parallel and distributed systems, 2006-12, Vol.17 (12), p.1377-1389
2006
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Sleepy Stack Leakage Reduction
IEEE transactions on very large scale integration (VLSI) systems, 2006-11, Vol.14 (11), p.1250-1263
2006
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A hardware-software real-time operating system framework for SoCs
IEEE design & test of computers, 2002-11, Vol.19 (6), p.44-51
2002
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Hardware/software partitioning of operating systems [SoC applications]
2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.338-339
2003
Open Access
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Timing analysis for preemptive multi-tasking real-time systems with caches
Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.1034-1039 Vol.2
2004
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PARLAK: parametrized lock cache generator
2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.1138-1139
2003
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Software streaming via block streaming
2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.912-917
2003
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A fast assembly level reverse execution method via dynamic slicing
Proceedings. 26th International Conference on Software Engineering, 2004, p.522-531
2004
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System-on-a-chip processor synchronization support in hardware
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.633-639
2001
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A novel O(n) parallel banker's algorithm for system-on-a-chip
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.2, p.1304-1308 Vol. 2
2005
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Path-based edge activation for dynamic run-time scheduling
Proceedings 12th International Symposium on System Synthesis, 1999, p.30-36
1999
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Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design
2006 IFIP International Conference on Very Large Scale Integration, 2006, p.367-372
2006
Open Access
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Round-robin arbiter design and generation
15th International Symposium on System Synthesis, 2002, 2002, p.243-248
2002
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A More Precise Model of Noise Based PCMOS Errors
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications, 2010, p.99-102
2010
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Energy minimization of a pipelined processor using a low voltage pipelined cache
Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002, 2002, Vol.1, p.67-73 vol.1
2002
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A debugger RTOS for embedded systems
Proceedings 27th EUROMICRO Conference. 2001: A Net Odyssey, 2001, p.264-269
2001
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A comparison of five different multiprocessor SoC bus architectures
Proceedings Euromicro Symposium on Digital Systems Design, 2001, p.202-209
2001
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A comparison of the RTU hardware RTOS with a hardware/software RTOS
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003, 2003, p.683-688
2003
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Hardware-software run-time systems and robotics: a case study
Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204), 1998, Vol.1, p.162-167 vol.1
1998
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Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
International Conference on Hardware Software Codesign: Proceedings of the tenth international symposium on Hardware/software codesign; 06-08 May 2002, 2002, p.79-84
2002
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A novel deadlock avoidance algorithm and its hardware implementation
International Conference on Hardware Software Codesign: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis; 08-10 Sept. 2004, 2004, p.200-205
2004
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A novel parallel deadlock detection algorithm and architecture
Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571), 2001, p.73-78
2001
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Interconnect delay aware RTL Verilog bus architecture generation for an SoC
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004, p.176-179
2004
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System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory
15th International Symposium on System Synthesis, 2002, 2002, p.225-230
2002
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