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Fabrication and Device Characterization of Omega-Shaped-Gate ZnO Nanowire Field-Effect Transistors

Nano letters, 2006-07, Vol.6 (7), p.1454-1458

2006

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A stacked memory device on logic 3D technology for ultra-high-density data storage

Nanotechnology, 2011-06, Vol.22 (25), p.254006-254006

2011

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Experimental investigation of the impact of LWR on sub-100-nm device performance

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.1984-1988

2004

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Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst

Applied physics letters, 2008-11, Vol.93 (18), p.182106-182106-3

2008

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Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Japanese Journal of Applied Physics, 2009-08, Vol.48 (8), p.8

2009

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Etching characteristics and modeling for oval-shaped contact

Thin solid films, 2007-04, Vol.515 (12), p.4923-4927

2007

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Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors

IEEE electron device letters, 2011-01, Vol.32 (1), p.81-83

2011

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Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

Japanese Journal of Applied Physics, 2011-01, Vol.50 (1), p.01AB06-01AB06-6

2011

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Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

2009 Symposium on VLSI Technology, 2009, p.186-187

2009

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Characterization of threshold voltage instability after program in charge trap flash memory

2009 IEEE International Reliability Physics Symposium, 2009, p.284-287

2009

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Effect of pre-existing void in sub-30nm Cu interconnect reliability

2010 IEEE International Reliability Physics Symposium, 2010, p.903-905

2010

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Gate oxide effect on wafer level reliability of next generation dram transistors

2010 IEEE International Reliability Physics Symposium, 2010, p.282-286

2010

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Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect

2009 IEEE International Reliability Physics Symposium, 2009, p.828-831

2009

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Electrical field dependence of data retention in high-k interpoly dielectrics

2009 IEEE International Reliability Physics Symposium, 2009, p.280-283

2009

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Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography

Japanese Journal of Applied Physics, 2004-06, Vol.43 (6S), p.3663

2004

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State of the art technologies and future prospective in display industry

2012 International Electron Devices Meeting, 2012, p.1.2.1-1.2.4

Joo-Tae Moon

2012

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Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

Solid-state electronics, 2011-02, Vol.56 (1), p.219-222

2011

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Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

Japanese Journal of Applied Physics, 2005-06, Vol.44 (6R), p.3828

2005

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High temperature platinum etching using Ti mask layer

Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 1999-07, Vol.17 (4), p.2151-2155

1999

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Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Solid-state electronics, 2005-03, Vol.49 (3), p.377-383

2005

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Selective Epitaxial Growth of Silicon for Vertical Diode Application

Japanese Journal of Applied Physics, 2010-08, Vol.49 (8), p.08JF03-08JF03-4

2010

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Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

Japanese Journal of Applied Physics, 2011-01, Vol.50 (1S1), p.1

2011

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Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

2007 IEEE Symposium on VLSI Technology, 2007, p.164-165

2007

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Converging lithography by combination of electrostatic layer-by-layer self-assembly and 193 nm photolithography: Top-down meets bottom-up

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2006-09, Vol.24 (5), p.2209-2213

2006

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Development and evaluation of highly efficient neutral beam source

Surface & coatings technology, 2007-08, Vol.201 (19), p.8601-8605

2007

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Fabrication and Device Characterization of Omega-Shaped-Gate ZnO Nanowire Field-Effect Transistors

A stacked memory device on logic 3D technology for ultra-high-density data storage

Experimental investigation of the impact of LWR on sub-100-nm device performance

Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Etching characteristics and modeling for oval-shaped contact

Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors

Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

Characterization of threshold voltage instability after program in charge trap flash memory

Effect of pre-existing void in sub-30nm Cu interconnect reliability

Gate oxide effect on wafer level reliability of next generation dram transistors

Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect

Electrical field dependence of data retention in high-k interpoly dielectrics

Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography

State of the art technologies and future prospective in display industry

Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

High temperature platinum etching using Ti mask layer

Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Selective Epitaxial Growth of Silicon for Vertical Diode Application

Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

Converging lithography by combination of electrostatic layer-by-layer self-assembly and 193 nm photolithography: Top-down meets bottom-up

Development and evaluation of highly efficient neutral beam source

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