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Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

IEEE transactions on electron devices, 2002-09, Vol.49 (9), p.1597-1605

2002

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1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

IEEE transactions on electron devices, 2003-04, Vol.50 (4), p.1001-1008

2003

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An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2410-2419

2000

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Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.691-700

1998

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Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

IEEE transactions on electron devices, 2001-06, Vol.48 (6), p.1165-1174

2001

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Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

IEEE transactions on electron devices, 2001-06, Vol.48 (6), p.1136-1144

2001

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Power Si-MOSFET operating with high efficiency under low supply voltage

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2385-2391

2000

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Thermal stability of CoSi/sub 2/ film for CMOS salicide

IEEE transactions on electron devices, 2000-11, Vol.47 (11), p.2208-2213

2000

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A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

IEEE transactions on electron devices, 1995-08, Vol.42 (8), p.1510-1521

1995

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Thermal stability of CoSi2 film for CMOS salicide

IEEE transactions on electron devices, 2000-11, Vol.47 (11), p.2208

2000

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Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008, p.559-562

2008

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0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.737-742

1998

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110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, p.156-157

2002

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Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration

IEEE transactions on electron devices, 1994-04, Vol.41 (4), p.546-552

1994

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Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.710-716

1998

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Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.126-129

Momose, H.S.

2008

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Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS

IEEE transactions on electron devices, 1994-06, Vol.41 (6), p.978-987

1994

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HfSiON gate dielectrics design for mixed signal CMOS

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.58-59

2005

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Ultra-thin chip with permalloy film for high performance MS/RF CMOS

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.220-221

2004

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0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.737-742

1998

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A hot-carrier degradation mechanism and electrical characteristics in S/sup 4/D n-MOSFET's

IEEE transactions on electron devices, 1997-11, Vol.44 (11), p.2053-2058

1997

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An improvement of hot-carrier reliability in the stacked nitride-oxide gate n- and p-MISFET's

IEEE transactions on electron devices, 1995-04, Vol.42 (4), p.704-712

1995

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High performance of silicided silicon-sidewall source and drain (S/sup 4/D) structure

IEEE transactions on electron devices, 1998-06, Vol.45 (6), p.1295-1299

1998

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0.15-μm buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.717-721

1998

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0.15-/spl mu/m buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

IEEE transactions on electron devices, 1998-03, Vol.45 (3), p.717-721

1998

Volltextzugriff (PDF)

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Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer

Power Si-MOSFET operating with high efficiency under low supply voltage

Thermal stability of CoSi/sub 2/ film for CMOS salicide

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

Thermal stability of CoSi2 film for CMOS salicide

Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate

Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel

Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS

HfSiON gate dielectrics design for mixed signal CMOS

Ultra-thin chip with permalloy film for high performance MS/RF CMOS

0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation

A hot-carrier degradation mechanism and electrical characteristics in S/sup 4/D n-MOSFET's

An improvement of hot-carrier reliability in the stacked nitride-oxide gate n- and p-MISFET's

High performance of silicided silicon-sidewall source and drain (S/sup 4/D) structure

0.15-μm buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

0.15-/spl mu/m buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

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