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Efficient Integer DCT Architectures for HEVC

IEEE transactions on circuits and systems for video technology, 2014-01, Vol.24 (1), p.168-178

2014

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FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2209-2220

2015

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Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT

IEEE transactions on circuits and systems for video technology, 2013-02, Vol.23 (2), p.353-363

2013

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VLSI Architecture for Signal, Speech, and Image Processing

First edition, 2023

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Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.695-703

Mohanty, Basant Kumar

2024

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Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

IEEE sensors journal, 2023-04, Vol.23 (7), p.1-1

Mohanty, Basant Kumar

2023

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Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform

IEEE transactions on circuits and systems for video technology, 2020-12, Vol.30 (12), p.4944-4952

Mohanty, Basant Kumar

2020

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Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer

IET circuits, devices & systems, 2013-11, Vol.7 (6), p.319-325

2013

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Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.165-174

Mohanty, Basant Kumar

2023

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Efficient Fixed-Width Adder-Tree Design

IEEE transactions on circuits and systems. II, Express briefs, 2019-02, Vol.66 (2), p.292-296

Mohanty, Basant Kumar

2019

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Area-Delay-Power Efficient Carry-Select Adder

IEEE transactions on circuits and systems. II, Express briefs, 2014-06, Vol.61 (6), p.418-422

2014

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Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation

IET image processing, 2014-06, Vol.8 (6), p.345-353

2014

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A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.444-452

2016

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An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1221-1229

2020

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Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

IEEE transactions on circuits and systems. I, Regular papers, 2015-01, Vol.62 (1), p.283-291

Mohanty, Basant Kumar

2015

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Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT

Circuits, systems, and signal processing, 2018-10, Vol.37 (10), p.4482-4503

2018

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Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

Circuits, systems, and signal processing, 2017-03, Vol.36 (3), p.1129-1149

2017

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An improved image processing scheme for automatic detection of harvested soybean seeds

Journal of food measurement & characterization, 2021-12, Vol.15 (6), p.5607-5621

2021

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Correction to: An improved image processing scheme for automatic detection of harvested soybean seeds

Journal of food measurement & characterization, 2021-12, Vol.15 (6), p.5759-5759

2021

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Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers

Circuits, systems, and signal processing, 2017-02, Vol.36 (2), p.447-473

2017

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Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data

IEEE transactions on circuits and systems. I, Regular papers, 2015-12, Vol.62 (12), p.2836-2845

2015

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Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

Journal of circuits, systems, and computers, 2016-07, Vol.25 (7), p.1650073

2016

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Efficient very large-scale integration architecture for variable length block least mean square adaptive filter

IET signal processing, 2015-10, Vol.9 (8), p.605-610

2015

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Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

Circuits, systems, and signal processing, 2016-08, Vol.35 (8), p.2958-2971

2016

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Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids

Circuits, systems, and signal processing, 2018-04, Vol.37 (4), p.1383-1406

2018

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Efficient Integer DCT Architectures for HEVC

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT

VLSI Architecture for Signal, Speech, and Image Processing

Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors

Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

Efficient Fixed-Width Adder-Tree Design

Area-Delay-Power Efficient Carry-Select Adder

Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT

Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

An improved image processing scheme for automatic detection of harvested soybean seeds

Correction to: An improved image processing scheme for automatic detection of harvested soybean seeds

Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

Efficient very large-scale integration architecture for variable length block least mean square adaptive filter

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids

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