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VLSI Architecture for Signal, Speech, and Image Processing

First edition, 2023

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A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

IEEE transactions on signal processing, 2013-02, Vol.61 (4), p.921-932

2013

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Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames

IEEE transactions on signal processing, 2011-11, Vol.59 (11), p.5605-5616

2011

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Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

IEEE transactions on signal processing, 2011-05, Vol.59 (5), p.2072-2084

2011

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LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1926-1935

2016

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Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

Circuits, systems, and signal processing, 2014-12, Vol.33 (12), p.3981-3994

2014

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Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT

IEEE transactions on circuits and systems for video technology, 2010-09, Vol.20 (9), p.1200-1209

2010

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Critical-path optimization for efficient hardware realization of lifting and flipping DWTs

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.1186-1189

2015

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Chronic kidney disease stage identification using texture analysis of ultrasound images

Biomedical signal processing and control, 2021-08, Vol.69, p.102695, Article 102695

2021

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Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT

Journal of low-power electronics, 2013-04, Vol.9 (1), p.37-44

2013

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A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage

Elektrik : Turkish journal of electrical engineering & computer sciences, 2023-01, Vol.31 (7), p.1237-1254

2023

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Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

IEEE transactions on circuits and systems. I, Regular papers, 2019-03, Vol.66 (3), p.1042-1050

2019

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Are–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

IEEE transactions on circuits and systems. I, Regular papers, 2019-01, Vol.66 (3), p.1042

2019

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Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters

IEEE transactions on circuits and systems. I, Regular papers, 2014-01, Vol.61 (1), p.120-133

2014

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Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

IEEE transactions on circuits and systems. II, Express briefs, 2012-07, Vol.59 (7), p.434-438

2012

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Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems

2015 IEEE International Conference on Digital Signal Processing (DSP), 2015, p.1266-1269

2015

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Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems

2015 IEEE International Conference on Digital Signal Processing (DSP), 2015, p.1270-1273

2015

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Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.2628-2631

2014

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Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank

2013 8th IEEE Design and Test Symposium, 2013, p.1-6

2013

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Efficient Systolic Architecture for VLSI Realization of 2-D Hartley-Like Transform

International journal of computers & applications, 2013-01, Vol.35 (1), p.22-28

2013

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EFFICIENT SYSTOLIC ARCHITECTURE FOR VLSI REALIZATION OF 2-D HARTLEY-LIKE TRANSFORM

International journal of computers & applications, 2013-01, Vol.35 (1), p.1-1

2013

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Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters

TENCON 2008 - 2008 IEEE Region 10 Conference, 2008, p.1-5

2008

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Design and Performance Analysis of Controlled DC-DC Converter

VLSI Architecture for Signal, Speech, and Image Processing, 2023, p.273-295

1, 2023

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Routing Strategy: Network-on-Chip Architectures

VLSI Architecture for Signal, Speech, and Image Processing, 2023, p.167-197

1, 2023

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Optimization of SOC Sub-Circuits Using Mathematical Modeling

VLSI Architecture for Signal, Speech, and Image Processing, 2023, p.221-251

1, 2023

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VLSI Architecture for Signal, Speech, and Image Processing

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT

Critical-path optimization for efficient hardware realization of lifting and flipping DWTs

Chronic kidney disease stage identification using texture analysis of ultrasound images

Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT

A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Are–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems

Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems

Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits

Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank

Efficient Systolic Architecture for VLSI Realization of 2-D Hartley-Like Transform

EFFICIENT SYSTOLIC ARCHITECTURE FOR VLSI REALIZATION OF 2-D HARTLEY-LIKE TRANSFORM

Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters

Design and Performance Analysis of Controlled DC-DC Converter

Routing Strategy: Network-on-Chip Architectures

Optimization of SOC Sub-Circuits Using Mathematical Modeling

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