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39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

Japanese Journal of Applied Physics, 2016-04, Vol.55 (4S), p.4

2016

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Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress

IEICE transactions on electronics, 2013, Vol.E96.C (6), p.759-765

2013

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NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM

IEICE transactions on electronics, 2013, Vol.E96.C (5), p.620-623

2013

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Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor

IEICE transactions on electronics, 2012, Vol.E95.C (4), p.564-571

2012

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A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

IEICE transactions on electronics, 2012, Vol.E95.C (4), p.572-578

2012

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Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, p.317-320

2012

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A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

IEEE journal of solid-state circuits, 2013-09, Vol.48 (9), p.2239-2249

2013

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Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

IEEE journal of solid-state circuits, 2011-09, Vol.46 (9), p.2180-2188

2011

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Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.924-931

2013

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Improvement of Read Margin and Its Distribution by [Formula Omitted] Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

IEEE journal of solid-state circuits, 2011-09, Vol.46 (9), p.2180

2011

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Improvement of Read Margin and Its Distribution by V rm TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

IEEE journal of solid-state circuits, 2011-09, Vol.46 (9), p.2180-2188

2011

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Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM

IEEE transactions on circuits and systems. I, Regular papers, 2012-08, Vol.59 (8), p.1635-1643

2012

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Improvement of Read Margin and Its Distribution by V Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

IEEE journal of solid-state circuits, 2011-09, Vol.46 (9), p.2180-2188

2011

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A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy

2012 IEEE International Solid-State Circuits Conference, 2012, p.232-234

2012

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Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.3B.6.1-3B.6.5

2013

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0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.236-237

2014

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Misleading energy and performance claims in sub/near threshold digital systems

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, p.625-631

2010

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Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

2010 Proceedings of ESSCIRC, 2010, p.354-357

2010

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Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI

2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), 2024, p.238-242

2024

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A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012, p.85-90

2012

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An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.582-637

2008

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Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)

IEEE transactions on electron devices, 1992-08, Vol.39 (8), p.1876-1881

1992

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39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Improvement of Read Margin and Its Distribution by [Formula Omitted] Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

Improvement of Read Margin and Its Distribution by V rm TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM

Improvement of Read Margin and Its Distribution by V Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy

Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

Misleading energy and performance claims in sub/near threshold digital systems

Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)

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