UB Paderborn / Katalog / Suche / in CDI

Cryptococcus laurentii fungemia in a low birth weight preterm neonate: India

Journal of infection and public health, 2018-11, Vol.11 (6), p.896-897

2018

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A case for dynamic frequency tuning in on-chip networks

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.292-303

2009

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IEEE_Xplore

RAFT: A router architecture with frequency tuning for on-chip networks

Journal of parallel and distributed computing, 2011-05, Vol.71 (5), p.625-640

2011

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Performance and power optimization through data compression in Network-on-Chip architectures

2008 IEEE 14th International Symposium on High Performance Computer Architecture, 2008, p.215-225

2008

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IEEE_Xplore

Scheduling techniques for GPU architectures with processing-in-memory capabilities

2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), 2016, p.31-44

2016

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Orchestrated scheduling and prefetching for GPGPUs

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.332-343

2013

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Opportunistic computing in GPU architectures

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.210-223

2019

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IEEE_Xplore

A heterogeneous multiple network-on-chip design: an application-aware approach

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-10

2013

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IEEE_Xplore

A case for heterogeneous on-chip interconnects for CMPs

2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, p.389-400

2011

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IEEE_Xplore

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs

DAC Design Automation Conference 2012, 2012, p.243-252

2012

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IEEE_Xplore

CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, 2010, p.1-12

2010

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IEEE_Xplore

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009, p.175-186

2009

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IEEE_Xplore

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

2008 International Symposium on Computer Architecture, 2008, p.251-261

2008

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IEEE_Xplore

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, p.69-80

2011

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IEEE_Xplore

Towards characterizing cloud backend workloads: insights from Google compute clusters

Performance evaluation review, 2010, Vol.37 (4), p.34-41

2010

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Runnemede: An architecture for Ubiquitous High-Performance Computing

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.198-209

2013

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IEEE_Xplore

PEPON: performance-aware hierarchical power budgeting for NoC based multicores

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012, p.65-74

2012

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OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance

SIGPLAN notices, 2013-04, Vol.48 (4), p.395-406

2013

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RAFT: A router architecture with frequency tuning for on-chip networks: Networks-on-Chip

Journal of parallel and distributed computing, 2011, Vol.71 (5), p.625-640

2011

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Application-aware prefetch prioritization in on-chip networks

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012, p.441-442

2012

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Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Computer architecture news, 2011-06, Vol.39 (3), p.69-80

2011

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OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance

Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems, 2013, p.395-406

2013

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Design and analysis of heterogeneous networks for chip-multiprocessors

Mishra, Asit K

2011

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ProQuest

Fine-grained accelerators for sparse machine learning workloads

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, p.635-640

2017

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IEEE_Xplore

Coordinated power management of voltage islands in CMPs

Performance evaluation review, 2010, Vol.38 (1), p.359-360

2010

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Cryptococcus laurentii fungemia in a low birth weight preterm neonate: India

A case for dynamic frequency tuning in on-chip networks

RAFT: A router architecture with frequency tuning for on-chip networks

Performance and power optimization through data compression in Network-on-Chip architectures

Scheduling techniques for GPU architectures with processing-in-memory capabilities

Orchestrated scheduling and prefetching for GPGPUs

Opportunistic computing in GPU architectures

A heterogeneous multiple network-on-chip design: an application-aware approach

A case for heterogeneous on-chip interconnects for CMPs

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs

CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Towards characterizing cloud backend workloads: insights from Google compute clusters

Runnemede: An architecture for Ubiquitous High-Performance Computing

PEPON: performance-aware hierarchical power budgeting for NoC based multicores

OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance

RAFT: A router architecture with frequency tuning for on-chip networks: Networks-on-Chip

Application-aware prefetch prioritization in on-chip networks

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance

Design and analysis of heterogeneous networks for chip-multiprocessors

Fine-grained accelerators for sparse machine learning workloads

Coordinated power management of voltage islands in CMPs

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