UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 72

Sortiert nach

Adaptive parallel decision deep neural network for high-speed equalization

Optics express, 2023-06, Vol.31 (13), p.22001-22011

2023

Link zum Volltext

Verfügbarkeit prüfen

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

IEEE access, 2022, Vol.10, p.96556-96567

2022

Link zum Volltext

Verfügbarkeit prüfen

Co-packaged optics (CPO): status, challenges, and solutions

Frontiers of Optoelectronics (Online), 2023-03, Vol.16 (1), p.1-1, Article 1

2023

Link zum Volltext

Verfügbarkeit prüfen

Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings

Journal of Computer Networks and Communications, 2018-01, Vol.2018, p.1-8

2018

Link zum Volltext

Verfügbarkeit prüfen

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

IEEE transactions on computers, 2014-03, Vol.63 (3), p.529-542

2014

Link zum Volltext
IEEE_Xplore

P3Stor： A parallel, durable flash-based SSD for enterprise-scale storage systems

Science China. Information sciences, 2011-06, Vol.54 (6), p.1129-1141

2011

Link zum Volltext

Verfügbarkeit prüfen

An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network

Science China. Information sciences, 2013-07, Vol.56 (7), p.235-254

2013

Link zum Volltext

Verfügbarkeit prüfen

Two-level tries: A general acceleration structure for parallel routing table accesses

Journal of Communications and Networks, 2011, 13(4), , pp.408-417

2011

Link zum Volltext
IEEE_Xplore

A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

Electronics (Basel), 2022-09, Vol.11 (18), p.2864

2022

Link zum Volltext

Verfügbarkeit prüfen

Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization

IEEE transactions on circuits and systems. I, Regular papers, 2024-04, Vol.71 (4), p.1-12

2024

Link zum Volltext
IEEE_Xplore

Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs

Optics express, 2022-07, Vol.30 (15), p.27333-27345

2022

Link zum Volltext

Verfügbarkeit prüfen

An Electro-Optic Mixed Structure Multiplier with an Optical Delay Accumulation Scheme in Time-Domain

Journal of lightwave technology, 2024-05, Vol.42 (10), p.3786-3798

2024

Link zum Volltext
IEEE_Xplore

Networks-on-Chip: From Implementations to Programming Paradigms

1, 2014

Link zum Volltext

Verfügbarkeit prüfen

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

Link zum Volltext
IEEE_Xplore

A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management

Neurocomputing (Amsterdam), 2020-06, Vol.393, p.126-141

2020

Link zum Volltext

Verfügbarkeit prüfen

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

IEEE transactions on circuits and systems. II, Express briefs, 2024-01, Vol.71 (1), p.1-1

2024

Link zum Volltext
IEEE_Xplore

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

Electronics (Basel), 2022-09, Vol.11 (18), p.2906

2022

Link zum Volltext

Verfügbarkeit prüfen

A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

Link zum Volltext
IEEE_Xplore

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology

Microelectronics, 2023-10, Vol.140, p.105905, Article 105905

2023

Link zum Volltext

Verfügbarkeit prüfen

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

2008 45th ACM/IEEE Design Automation Conference, 2008, p.630-633

2008

Link zum Volltext
IEEE_Xplore

A TLP approach for BGP based on local speculation

Science China. Information sciences, 2008-11, Vol.51 (11), p.1772-1784

2008

Link zum Volltext

Verfügbarkeit prüfen

Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

Link zum Volltext
IEEE_Xplore

An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

Link zum Volltext
IEEE_Xplore

A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

Electronics (Basel), 2023-08, Vol.12 (15), p.3237

2023

Link zum Volltext

Verfügbarkeit prüfen

An Improved Parallel Access Technology on Routing Table for Threaded BGP

2009 15th International Conference on Parallel and Distributed Systems, 2009, p.198-204

2009

Link zum Volltext
IEEE_Xplore

1 – 25 von 72

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(30)
Mit Volltextzugriff
(55)

Publikationsform

Sprache

Englisch
(71)
Koreanisch
(1)

Erscheinungsjahr

n.n

Neu hinzugefügt

... seit 30 Tagen
(3)
... seit 90 Tagen
(4)

Menü

Weitere Dienste

Einstellungen

Adaptive parallel decision deep neural network for high-speed equalization

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

Co-packaged optics (CPO): status, challenges, and solutions

Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

P3Stor： A parallel, durable flash-based SSD for enterprise-scale storage systems

An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network

Two-level tries: A general acceleration structure for parallel routing table accesses

A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization

Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs

An Electro-Optic Mixed Structure Multiplier with an Optical Delay Accumulation Scheme in Time-Domain

Networks-on-Chip: From Implementations to Programming Paradigms

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

A TLP approach for BGP based on local speculation

Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms

An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM

A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

An Improved Parallel Access Technology on Routing Table for Threaded BGP

Suchergebnisse filtern