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Design of heterogeneous MPSoC on FPGA

2007 7th International Conference on ASIC, 2007, p.102-105

2007

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A novel VLSI architecture of lum interpolator of H.264 decoder

2009 IEEE 8th International Conference on ASIC, 2009, p.175-178

2009

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DReNoC: A dynamically reconfigurable computing system based on network-on-chip

2009 IEEE 8th International Conference on ASIC, 2009, p.71-74

2009

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A mixed-signal calibration technology for the pipeline A/D converter

2009 IEEE 8th International Conference on ASIC, 2009, p.242-245

2009

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Calibration method considering second-order error term of timing skew for a novel multi-channel ADC

2011 9th IEEE International Conference on ASIC, 2011, p.949-952

2011

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A design of CMOS bandgap reference with low thermal drift and low offset

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.538-541

2008

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Design of AXI bus based MPSoC on FPGA

2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, 2009, p.560-564

2009

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True random number generator based on PLL

Dian zi yu xin xi xue bao = Journal of electronics & information technology, 2005-07, Vol.27 (7), p.1152-1156

2005

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Current switch driver and current source designs for high-speed current-steering DAC

2008 2nd International Conference on Anti-counterfeiting, Security and Identification, 2008, p.364-367

2008

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Design of an on-line configurable traffic generator for NoC

2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, 2009, p.556-559

2009

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Fractional-pel motion compensation interpolation architecture based on parallel FIR systolic arrays for H.264/AVC

2008 2nd International Conference on Anti-counterfeiting, Security and Identification, 2008, p.328-331

2008

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A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.818-821

2008

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On the Implementation of Virtual Array Using Configuration Plane

Advanced Parallel Processing Technologies, p.199-208

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Dual-ADC based digital calibration of timing skew for a time-interleaved ADC

2011 International Conference on Image Analysis and Signal Processing, 2011, p.42-45

2011

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Performance evaluation of cluster-based homogeneous multiprocessor system-on-chip using FPGA device

2010 2nd International Conference on Computer Engineering and Technology, 2010, Vol.4, p.V4-144-V4-147

2010

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Performance Evaluation of Cluster-Based Homogeneous Multiprocessor System-on-Chip Using FPGA Device

2009 Fourth International Conference on Embedded and Multimedia Computing, 2009, p.1-4

2009

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A high-performance sample-and-hold circuit for 14-bit 125MS/s pipelined ADC

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, p.424-426

2010

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Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.1264-1267

2008

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A multi-bit multiplying digital-to-analog converter with bi-directional overflow detection

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, p.427-429

2010

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Prototype design of cluster-based homogeneous Multiprocessor System-on-Chip

2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, 2009, p.311-315

2009

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VLSI Architecture of Video Post-Processing System for MPEG/H.26X

2009 Fifth International Joint Conference on INC, IMS and IDC, 2009, p.1520-1525

2009

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An Adaptive Dynamic Arbiter for Multi-Processor SoC

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.1993-1996

2006

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Design of a Hierarchy-Bus Based MPSoC on FPGA

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.1966-1968

2006

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Study on a low cost, high quality hybrid scaling algorithm

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.1969-1971

2006

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A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter

2007 7th International Conference on ASIC, 2007, p.703-706

2007

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Design of heterogeneous MPSoC on FPGA

A novel VLSI architecture of lum interpolator of H.264 decoder

DReNoC: A dynamically reconfigurable computing system based on network-on-chip

A mixed-signal calibration technology for the pipeline A/D converter

Calibration method considering second-order error term of timing skew for a novel multi-channel ADC

A design of CMOS bandgap reference with low thermal drift and low offset

Design of AXI bus based MPSoC on FPGA

True random number generator based on PLL

Current switch driver and current source designs for high-speed current-steering DAC

Design of an on-line configurable traffic generator for NoC

Fractional-pel motion compensation interpolation architecture based on parallel FIR systolic arrays for H.264/AVC

A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC

On the Implementation of Virtual Array Using Configuration Plane

Dual-ADC based digital calibration of timing skew for a time-interleaved ADC

Performance evaluation of cluster-based homogeneous multiprocessor system-on-chip using FPGA device

Performance Evaluation of Cluster-Based Homogeneous Multiprocessor System-on-Chip Using FPGA Device

A high-performance sample-and-hold circuit for 14-bit 125MS/s pipelined ADC

Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

A multi-bit multiplying digital-to-analog converter with bi-directional overflow detection

Prototype design of cluster-based homogeneous Multiprocessor System-on-Chip

VLSI Architecture of Video Post-Processing System for MPEG/H.26X

An Adaptive Dynamic Arbiter for Multi-Processor SoC

Design of a Hierarchy-Bus Based MPSoC on FPGA

Study on a low cost, high quality hybrid scaling algorithm

A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter

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