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Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.131-144

2008

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Dynamic recovery of negative bias temperature instability in p -type metal–oxide–semiconductor field-effect transistors

Applied physics letters, 2003-08, Vol.83 (8), p.1647-1649

2003

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Application-specific worst case corners using response surfaces and statistical models

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-09, Vol.24 (9), p.1372-1380

2005

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Degradation dynamics, recovery, and characterization of negative bias temperature instability

Microelectronics and reliability, 2005, Vol.45 (1), p.99-105

2005

Volltextzugriff (PDF)

Design for reliability

Microelectronics and reliability, 2000-08, Vol.40 (8-10), p.1285-1294

2000

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Modelling and simulation of reliability for design

Microelectronic engineering, 1999, Vol.49 (1), p.95-117

1999

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Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual, 2003, p.606-607

2003

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Direct parameter extraction for hot-carrier reliability simulation

Microelectronics and reliability, 1997-10, Vol.37 (10), p.1437-1440

1997

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An efficient control variates method for yield estimation of analog circuits based on a local model

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.415-421

2012

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Degradation dynamics, recovery, and characterization of negative bias temperature instability: Negative-Bias-Temperature Instability (NBTI) in MOS devices special sectio n

Microelectronics and reliability, 2005, Vol.45 (1), p.99-105

2005

Volltextzugriff (PDF)

Application specific worst case corners using response surfaces and statistical models

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), 2004, p.351-356

2004

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Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516), 2004, p.263-266

2004

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I.C. reliability simulation

Minehane, S

2000

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Characterization and modeling of MOSFET mismatch of a deep submicron technology

International Conference on Microelectronic Test Structures, 2003, 2003, p.238-243

2003

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Evolution of BSIM3v3 parameters during hot-carrier stress

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319), 1997, p.110-118

1997

Volltextzugriff (PDF)

On-wafer RF Figure-of-Merit Circuit Block Design for Technology Development, Process Control and PDK Validation

2007 IEEE International Conference on Microelectronic Test Structures, 2007, p.183-186

2007

Volltextzugriff (PDF)

Development of a direct SPICE parameter extraction strategy for hot-carrier reliability simulation

Minehane, S

1997

Volltextzugriff (PDF)

The application of a direct parameter extraction strategy to hot-carrier reliability simulation of n-channel LDD MOSFETs

1996 International Integrated Reliability Workshop Final Report, 1996, p.20-26

1996

Volltextzugriff (PDF)

Direct BSIM3v3 parameter extraction for hot-carrier reliability simulation of N-channel LDD MOSFETs

Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 1997, p.133-139

1997

Volltextzugriff (PDF)

Experiences on reliability simulation in the framework of the PROPHECY project : Special Section : EU Research Project Prophecy Papers

Microelectronics and reliability, 1999, Vol.39 (5), p.661-672

1999

Volltextzugriff (PDF)

Experiences on reliability simulation in the framework of the PROPHECY project

Microelectronics and reliability, 1999, Vol.39 (5), p.661-672

1999

Volltextzugriff (PDF)

Statistical Hot-Carrier Reliability Simulation using a Novel SPICE Parameter Evolution Model

30th European Solid-State Device Research Conference, 2000, p.616-619

2000

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Novel Parameter Extraction Techniques for Low-Voltage, Low-Power Technologies

29th European Solid-State Device Research Conference, 1999, Vol.1, p.452-455

1999

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The Consequences of Cold Water Immersion: Impacts and Treatment

International journal of aquatic research and education (Champaign, Ill.), 2019, Vol.11 (4)

2019

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Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies : Device technologies and circuit techniques for power management

IEEE transactions on electron devices, 2008, Vol.55 (1), p.131-144

2008

Volltextzugriff (PDF)

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Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

Dynamic recovery of negative bias temperature instability in p -type metal–oxide–semiconductor field-effect transistors

Application-specific worst case corners using response surfaces and statistical models

Degradation dynamics, recovery, and characterization of negative bias temperature instability

Design for reliability

Modelling and simulation of reliability for design

Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors

Direct parameter extraction for hot-carrier reliability simulation

An efficient control variates method for yield estimation of analog circuits based on a local model

Degradation dynamics, recovery, and characterization of negative bias temperature instability: Negative-Bias-Temperature Instability (NBTI) in MOS devices special sectio n

Application specific worst case corners using response surfaces and statistical models

Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

I.C. reliability simulation

Characterization and modeling of MOSFET mismatch of a deep submicron technology

Evolution of BSIM3v3 parameters during hot-carrier stress

On-wafer RF Figure-of-Merit Circuit Block Design for Technology Development, Process Control and PDK Validation

Development of a direct SPICE parameter extraction strategy for hot-carrier reliability simulation

The application of a direct parameter extraction strategy to hot-carrier reliability simulation of n-channel LDD MOSFETs

Direct BSIM3v3 parameter extraction for hot-carrier reliability simulation of N-channel LDD MOSFETs

Experiences on reliability simulation in the framework of the PROPHECY project : Special Section : EU Research Project Prophecy Papers

Experiences on reliability simulation in the framework of the PROPHECY project

Statistical Hot-Carrier Reliability Simulation using a Novel SPICE Parameter Evolution Model

Novel Parameter Extraction Techniques for Low-Voltage, Low-Power Technologies

The Consequences of Cold Water Immersion: Impacts and Treatment

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies : Device technologies and circuit techniques for power management

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