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All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3660-3671

2018

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A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2878-2882

2020

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A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2021-05, Vol.68 (5), p.1881-1891

2021

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A 180 mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT Using Self-Biasing Deep N-Well in 16-nm CMOS FinFET

IEEE solid-state circuits letters, 2018-07, Vol.1 (7), p.158-161

2018

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A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.448-450

2018

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14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, p.1-4

2013

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A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.52-443 vol.1

2002

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19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.332-333

2017

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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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A packet-memory-integrated 44Gb/s switching processor with a 10Gb port and 12Gb ports

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.34-388

2002

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All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

A 180 mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT Using Self-Biasing Deep N-Well in 16-nm CMOS FinFET

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

A packet-memory-integrated 44Gb/s switching processor with a 10Gb port and 12Gb ports

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