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A dc-pulsed capacitively coupled planar Langmuir probe for plasma process diagnostics and monitoring

Plasma sources science & technology, 2012-12, Vol.21 (6), p.65004-1-8

2012

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The SERS and TERS Effects Obtained by Gold Droplets on Top of Si Nanowires

Nano letters, 2007-01, Vol.7 (1), p.75-80

2007

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Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T56-T57

2015

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IEEE_Xplore

Integration aspects of strained Ge pFETs

Solid-state electronics, 2014-08, Vol.98, p.7-11

2014

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First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.5145-5150

2018

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IEEE_Xplore

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

Thin solid films, 2016-03, Vol.602, p.64-67

2016

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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T142-T143

2015

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IEEE_Xplore

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

IEEE transactions on electron devices, 2017-11, Vol.64 (11), p.4587-4593

2017

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IEEE_Xplore

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

Microelectronic engineering, 2018-05, Vol.192, p.14-18

2018

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SOI planar photonic crystal fabrication : Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Microelectronic engineering, 2005-07, Vol.81 (1), p.15-21

2005

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Plasma etching of proton-exchanged lithium niobate

Journal of vacuum science & technology. A, Vacuum, surfaces, and films, 2006-07, Vol.24 (4), p.1012-1015

2006

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Study on metrology of ERU tuning in TCP reactor, using PVx2 sensor wafer

2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2010, p.34-38

2010

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IEEE_Xplore

Relaxation of strain in patterned strained silicon investigated by UV Raman spectroscopy

Materials science & engineering. B, Solid-state materials for advanced technology, 2006-12, Vol.135 (3), p.184-187

2006

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Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

2013 IEEE International Electron Devices Meeting, 2013, p.20.4.1-20.4.4

2013

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IEEE_Xplore

The SOI planar photonic crystal fabrication: patterning of Cr using Cl2/O2 plasma etching

Microelectronic engineering, 2005-02, Vol.77 (2), p.139-143

2005

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Depth loading study in STI

2016 China Semiconductor Technology International Conference (CSTIC), 2016, p.1-2

2016

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Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

Russian microelectronics, 2016-05, Vol.45 (3), p.186-190

2016

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First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

2018 IEEE Symposium on VLSI Technology, 2018, p.193-194

2018

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IEEE_Xplore

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

2017 Symposium on VLSI Technology, 2017, p.T194-T195

2017

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Strain relaxation in nanopatterned strained silicon round pillars

Applied physics letters, 2007-01, Vol.90 (2), p.021902-021902-3

2007

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15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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IEEE_Xplore

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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IEEE_Xplore

Visible range whispering-gallery mode in microdisk array based on size-controlled Si nanocrystals

Applied physics letters, 2006-04, Vol.88 (15)

2006

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High-temperature resistant, ordered gold nanoparticle arrays

Nanotechnology, 2006-05, Vol.17 (9), p.2122-2126

2006

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Formation of the Co/Si(111)7×7 interface: AES- and EELS-study

Applied surface science, 2000-10, Vol.166 (1), p.125-129

2000

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A dc-pulsed capacitively coupled planar Langmuir probe for plasma process diagnostics and monitoring

The SERS and TERS Effects Obtained by Gold Droplets on Top of Si Nanowires

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Integration aspects of strained Ge pFETs

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

SOI planar photonic crystal fabrication : Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Plasma etching of proton-exchanged lithium niobate

Study on metrology of ERU tuning in TCP reactor, using PVx2 sensor wafer

Relaxation of strain in patterned strained silicon investigated by UV Raman spectroscopy

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

The SOI planar photonic crystal fabrication: patterning of Cr using Cl2/O2 plasma etching

Depth loading study in STI

Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

Strain relaxation in nanopatterned strained silicon round pillars

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

Visible range whispering-gallery mode in microdisk array based on size-controlled Si nanocrystals

High-temperature resistant, ordered gold nanoparticle arrays

Formation of the Co/Si(111)7×7 interface: AES- and EELS-study

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