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Cost-Effective Testing Solutions for Sealing Material With IR Package

IEEE transactions on components, packaging, and manufacturing technology (2011), 2018-09, Vol.8 (9), p.1672-1677

2018

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IEEE_Xplore

Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-11, Vol.7 (11), p.1774-1785

2017

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IEEE_Xplore

High Density TSV-Free Interposer (TFI) Packaging with Submicron Cu Damascene RDLs for Integration of CPU/GPU and HBM

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.1885-1892

2018

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IEEE_Xplore

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.1879-1885

2016

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Molding process development for Low-Cost MEMS-WLCSP with silicon pillars and Cu wires as vertical interconnections

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), 2017, p.1-6

2017

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IEEE_Xplore

High temperature endurable die attach material for power electronics package - Process challenges

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), 2017, p.1-5

2017

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IEEE_Xplore

Comprehensive Investigation of Die Shift in Compression Molding Process for 12 Inch Fan-Out Wafer Level Packaging

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.1605-1610

2016

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Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.1196-1203

2017

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IEEE_Xplore

Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.13-18

2016

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High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.1-5

2016

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MEMS WLCSP development using vertical interconnection

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.455-458

2016

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Drop impact reliability study of high density fan-out wafer level package

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.771-778

2016

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Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-8

2015

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Design and optimization of molding process for MEMS WLSCP

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.370-375

2016

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Gold-germanium laser jetting for high temperature (300°C) flip chip application

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.487-491

2014

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Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.435-440

2016

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Assembly Process and Warpage Management of Large Size through Silicon Interposer (38.7mm × 26.7mm) Package

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.1892-1898

2016

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2.5D through silicon interposer package fabrication by chip-on-wafer (CoW) approach

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.679-683

2014

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Mitigation of warpage for large 2.5D Through Silicon Interposer (TSI) package assembly

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-6

2015

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Miniaturization of bio-fluidic package for point-of-care diagnostic

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-4

2015

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Integrated electronic and microfluidic packaging for CMOS biosensor chip

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.713-718

2014

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Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300°c/30kpsi) applications

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013), 2013, p.335-340

2013

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Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013), 2013, p.424-429

2013

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Development of fluxless flip chip reflow process for high density flip chip interconnect

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-6

2015

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Process characterization of highly conductive silver paste die attach materials for thin die on QFN

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012, p.372-378

2012

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IEEE_Xplore

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Cost-Effective Testing Solutions for Sealing Material With IR Package

Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling

High Density TSV-Free Interposer (TFI) Packaging with Submicron Cu Damascene RDLs for Integration of CPU/GPU and HBM

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

Molding process development for Low-Cost MEMS-WLCSP with silicon pillars and Cu wires as vertical interconnections

High temperature endurable die attach material for power electronics package - Process challenges

Comprehensive Investigation of Die Shift in Compression Molding Process for 12 Inch Fan-Out Wafer Level Packaging

Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package

Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL

High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging

MEMS WLCSP development using vertical interconnection

Drop impact reliability study of high density fan-out wafer level package

Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology

Design and optimization of molding process for MEMS WLSCP

Gold-germanium laser jetting for high temperature (300°C) flip chip application

Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

Assembly Process and Warpage Management of Large Size through Silicon Interposer (38.7mm × 26.7mm) Package

2.5D through silicon interposer package fabrication by chip-on-wafer (CoW) approach

Mitigation of warpage for large 2.5D Through Silicon Interposer (TSI) package assembly

Miniaturization of bio-fluidic package for point-of-care diagnostic

Integrated electronic and microfluidic packaging for CMOS biosensor chip

Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300°c/30kpsi) applications

Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer

Development of fluxless flip chip reflow process for high density flip chip interconnect

Process characterization of highly conductive silver paste die attach materials for thin die on QFN

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