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Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation

Journal of applied physics, 2014-01, Vol.115 (4), p.44505

2014

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Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

IEEE transactions on electron devices, 2006-05, Vol.53 (5), p.1039-1047

2006

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Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

IEEE transactions on electron devices, 2010-01, Vol.57 (1), p.256-262

2010

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Investigation on Molybdenum and Its Conductive Oxides as p-Type Metal Gate Candidates

Journal of the Electrochemical Society, 2008, Vol.155 (7), p.H481

2008

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Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

IEEE transactions on electron devices, 2012-02, Vol.59 (2), p.292-301

2012

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Vertical GAAFETs for the Ultimate CMOS Scaling

IEEE transactions on electron devices, 2015-05, Vol.62 (5), p.1433-1439

2015

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Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

IEEE electron device letters, 2015-06, Vol.36 (6), p.600-602

2015

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pMOSFET with 200% mobility enhancement induced by multiple stressors

IEEE electron device letters, 2006-06, Vol.27 (6), p.511-513

2006

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Modeling the impact of junction angles in tunnel field-effect transistors

Solid-state electronics, 2012-03, Vol.69, p.31-37

2012

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A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

IEEE electron device letters, 2014-09, Vol.35 (9), p.957-959

2014

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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact

IEEE transactions on electron devices, 2016-07, Vol.63 (7), p.2671-2676

2016

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Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

IEEE transactions on electron devices, 2006-06, Vol.53 (6), p.1398-1404

2006

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Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

IEEE electron device letters, 2010-06, Vol.31 (6), p.549-551

2010

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Lanthanum and Lanthanum Silicide Contacts on N-Type Silicon

IEEE electron device letters, 2017-07, Vol.38 (7), p.843-846

2017

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Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

IEEE electron device letters, 2016-04, Vol.37 (4), p.482-485

2016

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Electrical TCAD Simulations of a Germanium pMOSFET Technology

IEEE transactions on electron devices, 2010-10, Vol.57 (10), p.2539-2546

2010

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A model determining optimal doping concentration and material's band gap of tunnel field-effect transistors

Applied physics letters, 2012-05, Vol.100 (19), p.193509-193509-4

2012

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On the distribution of oxide defect levels in Al2O3 and HfO2 high-k dielectrics deposited on InGaAs metal-oxide-semiconductor devices studied by capacitance-voltage hysteresis

Journal of applied physics, 2017-04, Vol.121 (14)

2017

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Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks

Applied physics letters, 2015-11, Vol.107 (22)

2015

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Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

Journal of applied physics, 2014-12, Vol.116 (21)

2014

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(Invited) Vertical Nanowire FET Integration and Device Aspects

ECS transactions, 2016-05, Vol.72 (4), p.31-42

2016

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Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

IEEE transactions on electron devices, 2006-07, Vol.53 (7), p.1657-1668

2006

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TiSi(Ge) Contacts Formed at Low Temperature Achieving Around 2 \,\, \times \,\, 10^}~\Omega cm2 Contact Resistivities to p-SiGe

IEEE transactions on electron devices, 2017-02, Vol.64 (2), p.500-506

2017

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Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

IEEE transactions on electron devices, 2006-07, Vol.53 (7), p.1647-1656

2006

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Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1446-1453

2007

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Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation

Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Investigation on Molybdenum and Its Conductive Oxides as p-Type Metal Gate Candidates

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Vertical GAAFETs for the Ultimate CMOS Scaling

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

pMOSFET with 200% mobility enhancement induced by multiple stressors

Modeling the impact of junction angles in tunnel field-effect transistors

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

Lanthanum and Lanthanum Silicide Contacts on N-Type Silicon

Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

Electrical TCAD Simulations of a Germanium pMOSFET Technology

A model determining optimal doping concentration and material's band gap of tunnel field-effect transistors

On the distribution of oxide defect levels in Al2O3 and HfO2 high-k dielectrics deposited on InGaAs metal-oxide-semiconductor devices studied by capacitance-voltage hysteresis

Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks

Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

(Invited) Vertical Nanowire FET Integration and Device Aspects

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

TiSi(Ge) Contacts Formed at Low Temperature Achieving Around 2 \,\, \times \,\, 10^}~\Omega cm2 Contact Resistivities to p-SiGe

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

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