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Latch Susceptibility to Transient Faults and New Hardening Approach

IEEE transactions on computers, 2007-09, Vol.56 (9), p.1255-1268

2007

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Low-Cost Strategy for Bus Propagation Delay Reduction

Journal of electronic testing, 2019-04, Vol.35 (2), p.253-260

2019

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Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness

IEEE transactions on emerging topics in computing, 2018-10, Vol.6 (4), p.488-497

2018

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Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

Journal of electronic testing, 2008-06, Vol.24 (1-3), p.297-311

2008

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Modeling Crosstalk Effects in CNT Bus Architectures

IEEE transactions on nanotechnology, 2007-03, Vol.6 (2), p.133-145

2007

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Accurate Linear Model for SET Critical Charge Estimation

IEEE transactions on very large scale integration (VLSI) systems, 2009-08, Vol.17 (8), p.1161-1166

2009

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Inverters' self-checking monitors for reliable photovoltaic systems

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.672-677

2016

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Testing Resistive Opens and Bridging Faults Through Pulse Propagation

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-06, Vol.28 (6), p.915-925

2009

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TMR voting in the presence of crosstalk faults at the voter inputs

IEEE transactions on reliability, 2004-09, Vol.53 (3), p.342-348

2004

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Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2322-2325

2011

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Clock Faults Induced Min and Max Delay Violations

Journal of electronic testing, 2014-02, Vol.30 (1), p.111-123

2014

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Implications of clock distribution faults and issues with screening them during manufacturing testing

IEEE transactions on computers, 2004-05, Vol.53 (5), p.531-546

2004

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Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Journal of electronic testing, 2013-06, Vol.29 (3), p.401-413

2013

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Power Consumption of Fault Tolerant Busses

IEEE transactions on very large scale integration (VLSI) systems, 2008-05, Vol.16 (5), p.542-553

2008

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Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines

IEEE transactions on computers, 2000-06, Vol.49 (6), p.560-574

2000

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Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection

2022 IEEE 23rd Latin American Test Symposium (LATS), 2022, p.1-6

2022

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Low Cost NBTI Degradation Detection and Masking Approaches

IEEE transactions on computers, 2013-03, Vol.62 (3), p.496-509

2013

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Multiple transient faults in logic: an issue for next generation ICs?

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005, p.352-360

2005

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Novel on-chip circuit for jitter testing in high-speed PLLs

IEEE transactions on instrumentation and measurement, 2005-10, Vol.54 (5), p.1779-1788

2005

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Low cost and high speed embedded two-rail code checker

IEEE transactions on computers, 2005-02, Vol.54 (2), p.153-164

2005

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Novel transient fault hardened static latch

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.886-892

2003

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Concurrent detection of power supply noise

IEEE transactions on reliability, 2003-12, Vol.52 (4), p.469-475

2003

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Error Correcting Strategy for High Speed and High Density Reliable Flash Memories

Journal of electronic testing, 2003-10, Vol.19 (5), p.511

2003

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Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)

IEEE transactions on computers, 2006-02, Vol.55 (2), p.97-98

2006

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On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.265-272

2010

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Latch Susceptibility to Transient Faults and New Hardening Approach

Low-Cost Strategy for Bus Propagation Delay Reduction

Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

Modeling Crosstalk Effects in CNT Bus Architectures

Accurate Linear Model for SET Critical Charge Estimation

Inverters' self-checking monitors for reliable photovoltaic systems

Testing Resistive Opens and Bridging Faults Through Pulse Propagation

TMR voting in the presence of crosstalk faults at the voter inputs

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

Clock Faults Induced Min and Max Delay Violations

Implications of clock distribution faults and issues with screening them during manufacturing testing

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Power Consumption of Fault Tolerant Busses

Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines

Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection

Low Cost NBTI Degradation Detection and Masking Approaches

Multiple transient faults in logic: an issue for next generation ICs?

Novel on-chip circuit for jitter testing in high-speed PLLs

Low cost and high speed embedded two-rail code checker

Novel transient fault hardened static latch

Concurrent detection of power supply noise

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories

Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

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