UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

CMOS 65 nm 'on chip' broadband real time substrate noise measurement

Electronics letters, 2015-10, Vol.51 (21), p.1710-1711

2015

Volltextzugriff (PDF)

Wide-band substrate crosstalk sensor for wireless SoC applications

Sensors and actuators. A. Physical., 2016-03, Vol.239, p.144-152

2016

Volltextzugriff (PDF)

A single-chip digitally calibrated 5.15~5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN

IEEE journal of solid-state circuits, 2003-12, Vol.38 (12), p.2221-2231

2003

Volltextzugriff (PDF)

Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2889-2899

2002

Volltextzugriff (PDF)

Power efficient data path synthesis of sum-of-products computations

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.446-450

2003

Volltextzugriff (PDF)

Power Efficient Hierarchical Scheduling for DSP Transformations

VLSI Design, 2002, Vol.2002 (2), p.203-217

2002

Volltextzugriff (PDF)

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.492-497

1999

Volltextzugriff (PDF)

A novel algorithm for low-power image and video coding

IEEE transactions on circuits and systems for video technology, 1998-06, Vol.8 (3), p.258-263

1998

Volltextzugriff (PDF)

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

VLSI Design, 1999-01, Vol.1998 (2), p.177-202

1999

Volltextzugriff (PDF)

Low power architectures for digital signal processing

Journal of systems architecture, 2000-04, Vol.46 (7), p.551-571

2000

Volltextzugriff (PDF)

A power grid analysis and verification tool based on a Statistical Prediction Engine

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010, p.839-842

2010

Volltextzugriff (PDF)

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-[micro]m CMOS transceiver for 802.11a/b/g wireless LAN

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1180

2004

Volltextzugriff (PDF)

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1180-1184

2004

Volltextzugriff (PDF)

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-mum CMOS transceiver for 802.11a/b/g wireless LAN

IEEE journal of solid-state circuits, 2004-07, Vol.39 (7), p.1180-1184

2004

Volltextzugriff (PDF)

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18- mu m CMOS transceiver for 802.11a/b/g wireless LAN

IEEE journal of solid-state circuits, 2004-01, Vol.39 (7)

2004

Volltextzugriff (PDF)

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-[micro]m CMOS transceiver for 802.11a wireless LAN

IEEE journal of solid-state circuits, 2003-12, Vol.38 (12), p.2221

2003

Volltextzugriff (PDF)

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

IEEE journal of solid-state circuits, 2003-12, Vol.38 (12), p.2221-2231

2003

Volltextzugriff (PDF)

Optimisation techniques for reducing global bus switching activity in realisations of sum-of-products computations in DSP systems

IEE proceedings. Circuits, devices, and systems, 2003-02, Vol.150 (1), p.16

2003

Volltextzugriff (PDF)

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-mum CMOS transceiver for 802.11a wireless LAN

IEEE journal of solid-state circuits, 2003-12, Vol.38 (12), p.2221-2231

2003

Volltextzugriff (PDF)

Accurate data path models for fast RT-level power estimation

IEE proceedings. Computers and digital techniques, 2000-07, Vol.147 (4), p.209

2000

Volltextzugriff (PDF)

Low power synthesis of sum-of-products computation (poster session)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514), 2000, p.234-237

2000

Volltextzugriff (PDF)

Novel vector quantization based algorithms for low-power image coding and decoding

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1999-02, Vol.46 (2), p.193-198

1999

Volltextzugriff (PDF)

A novel methodology for power consumption reduction in a class of DSP algorithms

1998 IEEE International Symposium on Circuits and Systems (ISCAS), 1998, Vol.6, p.199-202 vol.6

1998

Volltextzugriff (PDF)

Computation reordering: A novel transformation for low power DSP synthesis

VLSI design (Yverdon, Switzerland), 2000-01, Vol.10 (2), p.177-202

2000

Volltextzugriff (PDF)

Low-power image decoding using fractals

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, Vol.2, p.748-751 vol.2

1996

Volltextzugriff (PDF)

1 – 25 von 51

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(24)
Mit Volltextzugriff
(46)

Publikationsform

Sprache

Englisch
(51)

Erscheinungsjahr

n.n

Menü

Weitere Dienste

Einstellungen

CMOS 65 nm 'on chip' broadband real time substrate noise measurement

Wide-band substrate crosstalk sensor for wireless SoC applications

A single-chip digitally calibrated 5.15~5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Power efficient data path synthesis of sum-of-products computations

Power Efficient Hierarchical Scheduling for DSP Transformations

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

A novel algorithm for low-power image and video coding

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

Low power architectures for digital signal processing

A power grid analysis and verification tool based on a Statistical Prediction Engine

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-[micro]m CMOS transceiver for 802.11a/b/g wireless LAN

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-mum CMOS transceiver for 802.11a/b/g wireless LAN

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18- mu m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-[micro]m CMOS transceiver for 802.11a wireless LAN

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

Optimisation techniques for reducing global bus switching activity in realisations of sum-of-products computations in DSP systems

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-mum CMOS transceiver for 802.11a wireless LAN

Accurate data path models for fast RT-level power estimation

Low power synthesis of sum-of-products computation (poster session)

Novel vector quantization based algorithms for low-power image coding and decoding

A novel methodology for power consumption reduction in a class of DSP algorithms

Computation reordering: A novel transformation for low power DSP synthesis

Low-power image decoding using fractals

Suchergebnisse filtern