UB Paderborn / Katalog / Suche / in CDI

BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.732-746

2024

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Development of a modular photoreactor for the upscaling of continuous flow photochemistry

Reaction chemistry & engineering, 2022-10, Vol.7 (11), p.228-2284

2022

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Power Challenges Caused by IOT Edge Nodes: Securing and Sensing Our World

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, p.17-22

2019

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Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.42-51

2012

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Digital Systems Power Management for High Performance Mixed Signal Platforms

IEEE transactions on circuits and systems. I, Regular papers, 2014-04, Vol.61 (4), p.961-975

2014

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Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

IEEE journal of solid-state circuits, 2009-02, Vol.44 (2), p.484-494

2009

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A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias

2011 Proceedings of the ESSCIRC (ESSCIRC), 2011, p.379-382

2011

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Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

Proceedings of the conference on Design, Automation & Test in Europe, 2014, p.1-2

2014

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Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, p.1-2

2014

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Characterization of STI Edge Effects on CMOS Variability

IEEE transactions on semiconductor manufacturing, 2009-02, Vol.22 (1), p.59-65

2009

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Artifact: End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches

2024 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops), 2024, p.5-6

2024

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End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches

2024 IEEE International Conference on Pervasive Computing and Communications (PerCom), 2024, p.18-24

2024

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Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

2010 International Conference on Microelectronic Test Structures (ICMTS), 2010, p.182-187

2010

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CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, p.1-8

2023

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A forward body bias generator for digital CMOS circuits with supply voltage scaling

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.2482-2485

2010

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Influence of STI stress on drain current matching in advanced CMOS

2008 IEEE International Conference on Microelectronic Test Structures, 2008, p.238-243

2008

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An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2005, p.187-196

2005

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Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.675-676

2004

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Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, p.325-329

2005

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Limits to performance spread tuning using adaptive voltage and body biasing

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5-8 Vol. 1

2005

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Reducing Cross-Talk Induced Power Consumption and Delay

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2004, p.179-188

2004

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Aggressor aware repeater circuits for improving on-chip bus performance and robustness

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003, p.261-264

2003

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Body bias driven design synthesis for optimum performance per area

2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, p.472-477

2010

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Post-silicon tuning capabilities of 45nm low-power CMOS digital circuits

2009 Symposium on VLSI Circuits, 2009, p.110-111

2009

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A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits

2009 14th IEEE European Test Symposium, 2009, p.135-140

2009

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BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration

Development of a modular photoreactor for the upscaling of continuous flow photochemistry

Power Challenges Caused by IOT Edge Nodes: Securing and Sensing Our World

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Digital Systems Power Management for High Performance Mixed Signal Platforms

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

Characterization of STI Edge Effects on CMOS Variability

Artifact: End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches

End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Influence of STI stress on drain current matching in advanced CMOS

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits

Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs

Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication

Limits to performance spread tuning using adaptive voltage and body biasing

Reducing Cross-Talk Induced Power Consumption and Delay

Aggressor aware repeater circuits for improving on-chip bus performance and robustness

Body bias driven design synthesis for optimum performance per area

Post-silicon tuning capabilities of 45nm low-power CMOS digital circuits

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits

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