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Placement and routing tools for the Triptych FPGA

IEEE transactions on very large scale integration (VLSI) systems, 1995-12, Vol.3 (4), p.473-482

1995

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Distributed-memory parallel routing for field-programmable gate arrays

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-08, Vol.19 (8), p.850-862

2000

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RADAR - reconfigurable analog and digital array for radiation-hardened circuits

2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720), 2004, Vol.4, p.2417-2426 Vol.4

2004

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PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

Third International ACM Symposium on Field-Programmable Gate Arrays, 1995, p.111-117

1995

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A high-performance 64-bit adder implemented in output prediction logic

Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001, 2001, p.213-222

2001

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Output prediction logic: a high-performance CMOS design technique

Proceedings 2000 International Conference on Computer Design, 2000, p.247-254

2000

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Experiences with the MacTester in computer science and engineering education

IEEE transactions on education, 1997-02, Vol.40 (1), p.12-21

1997

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A 64b adder using self-calibrating differential output prediction logic

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.1745-1754

2006

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A high performance CMOS programmable logic core

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004, p.439-442

2004

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WTA - Waveform-based Timing Analysis for deep submicron circuits

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002, 2002, p.625-631

2002

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SEE-Hardened-by-Design Area-Efficient SRAMs

2005 IEEE Aerospace Conference, 2005, p.1-7

2005

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Application of output prediction logic to differential CMOS

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.57-65

2001

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Mitigation of Single-and Multiple-Cycle-Duration SETs using Double-Mode-Redundancy (DMR) in Time

2005 IEEE Aerospace Conference, 2005, p.1-10

2005

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409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005, p.52-58

2005

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Emerald - An Architecture-Driven Tool Compiler for FPGAs

Fourth International ACM Symposium on Field-Programmable Gate Arrays, 1996, p.144-150

1996

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Configuration interaction calculations on the planar 1(π,π) state of ethylene

The Journal of chemical physics, 1977-04, Vol.66 (7), p.2959-2971

1977

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Apex: two architectures for generating parametric curves and surfaces

The Visual computer, 1989-09, Vol.5 (5), p.264-276

1989

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Hybrid compiled/interpreted simulation of MOS circuits

Proceedings of the European Conference on Design Automation, 1991, p.558-564

1991

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ESR investigation of matrix isolated B 16O and B 17O radicals: Comparison of nuclear hyperfine structure with a b i n i t i o calculations

The Journal of chemical physics, 1982-01, Vol.76 (1), p.126-136

1982

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A notation for describing multiple views of VLSI circuits

25th ACM/IEEE, Design Automation Conference.Proceedings 1988, 1988, p.102-107

1988

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Singlet Rydberg states of ethylene

The Journal of chemical physics, 1977-12, Vol.67 (12), p.5613-5618

1977

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A theoretical determination of the electron affinity of methylene

The Journal of chemical physics, 1982-01, Vol.77 (12), p.6134-6143

1982

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ChemInform Abstract: THE BK METHOD: APPLICATION TO METHYLENE

Chemischer Informationsdienst, 1981-09, Vol.12 (35)

1981

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The role of spin inversion in the triplet photochemistry of benzyl halides and benzylammonium salts

Journal of organic chemistry, 1980-04, Vol.45 (8), p.1388-1393

1980

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Long-term benefits and adverse effects of intermittent versus daily glucocorticoids in boys with Duchenne muscular dystrophy

Journal of neurology, neurosurgery and psychiatry, 2013-06, Vol.84 (6), p.698-705

2013

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Placement and routing tools for the Triptych FPGA

Distributed-memory parallel routing for field-programmable gate arrays

RADAR - reconfigurable analog and digital array for radiation-hardened circuits

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

A high-performance 64-bit adder implemented in output prediction logic

Output prediction logic: a high-performance CMOS design technique

Experiences with the MacTester in computer science and engineering education

A 64b adder using self-calibrating differential output prediction logic

A high performance CMOS programmable logic core

WTA - Waveform-based Timing Analysis for deep submicron circuits

SEE-Hardened-by-Design Area-Efficient SRAMs

Application of output prediction logic to differential CMOS

Mitigation of Single-and Multiple-Cycle-Duration SETs using Double-Mode-Redundancy (DMR) in Time

409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

Emerald - An Architecture-Driven Tool Compiler for FPGAs

Configuration interaction calculations on the planar 1(π,π) state of ethylene

Apex: two architectures for generating parametric curves and surfaces

Hybrid compiled/interpreted simulation of MOS circuits

ESR investigation of matrix isolated B 16O and B 17O radicals: Comparison of nuclear hyperfine structure with a b i n i t i o calculations

A notation for describing multiple views of VLSI circuits

Singlet Rydberg states of ethylene

A theoretical determination of the electron affinity of methylene

ChemInform Abstract: THE BK METHOD: APPLICATION TO METHYLENE

The role of spin inversion in the triplet photochemistry of benzyl halides and benzylammonium salts

Long-term benefits and adverse effects of intermittent versus daily glucocorticoids in boys with Duchenne muscular dystrophy

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