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Theory of latency-insensitive design

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-09, Vol.20 (9), p.1059-1076

2001

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A methodology for hardware verification using compositional model checking

Science of computer programming, 2000-05, Vol.37 (1), p.279-309

McMillan, K.L.

2000

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An interpolating theorem prover

Theoretical computer science, 2005-11, Vol.345 (1), p.101-121

McMillan, K.L.

2005

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Sibling-substitution-based BDD minimization using don't cares

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-01, Vol.19 (1), p.44-55

2000

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Symbolic model checking for sequential circuit verification

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-04, Vol.13 (4), p.401-424

1994

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Symbolic model checking : 1020 states and beyond

Information and computation, 1992-06, Vol.98 (2), p.142-170

1992

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Approximation and decomposition of binary decision diagrams

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.445-450

1998

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Safe BDD Minimization Using Don't Cares

Proceedings - ACM IEEE Design Automation Conference, 1997, p.208-213

1997

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A Structural Induction Theorem for Processes

Information and computation, 1995-02, Vol.117 (1), p.1-11

1995

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Spectral transforms for large boolean functions with applications to technology mapping

30th ACM/IEEE Design Automation Conference, 1993, p.54-60

1993

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Some strategies for proving theorems with a model checker abstract of invited talk

Proceedings Fifteenth Annual IEEE Symposium on Logic in Computer Science (Cat. No.99CB36332), 2000, p.305-306

McMillan, K.L.

2000

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Analysis of digital circuits through symbolic reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 1991-11, Vol.10 (11), p.1356-1371

1991

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A methodology for correct-by-construction latency insensitive design

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 1999, p.309-315

1999

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A language for compositional specification and verification of finite state hardware controllers

Proceedings of the IEEE, 1991-09, Vol.79 (9), p.1283-1292

1991

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Fitting formal methods into the design cycle

31st Design Automation Conference, 1994, p.314-319

McMillan, K. L.

1994

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Symbolic model checking: 10 20 States and beyond

Information and computation, 1992, Vol.98 (2), p.142-170

1992

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Probabilistic state space search

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 1999, p.574-579

1999

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Methods for exploiting SAT solvers in unbounded model checking

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings, 2003, p.135-142

McMillan, K.L.

2003

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Sequential circuit verification using symbolic model checking

27th ACM/IEEE Design Automation Conference, 1990, p.46-51

1990

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Engineering change in a non-deterministic FSM setting

33rd Design Automation Conference Proceedings, 1996, 1996, p.451-456

1996

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Fast discrete function evaluation using decision diagrams

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995, p.402-407

1995

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Algorithms for interface timing verification

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1992, p.48-51

1992

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Symbolic model checking: 10/sup 20/ states and beyond

[1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science, 1990, p.428-439

1990

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Patterns of NPP, GPP, respiration, and NEP during boreal forest succession

Global change biology, 2011-02, Vol.17 (2), p.855-871

2011

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Development and Validation of a Kinetic Model for Enzymatic Saccharification of Lignocellulosic Biomass

Biotechnology progress, 2004-05, Vol.20 (3), p.698-705

2004

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Theory of latency-insensitive design

A methodology for hardware verification using compositional model checking

An interpolating theorem prover

Sibling-substitution-based BDD minimization using don't cares

Symbolic model checking for sequential circuit verification

Symbolic model checking : 1020 states and beyond

Approximation and decomposition of binary decision diagrams

Safe BDD Minimization Using Don't Cares

A Structural Induction Theorem for Processes

Spectral transforms for large boolean functions with applications to technology mapping

Some strategies for proving theorems with a model checker abstract of invited talk

Analysis of digital circuits through symbolic reduction

A methodology for correct-by-construction latency insensitive design

A language for compositional specification and verification of finite state hardware controllers

Fitting formal methods into the design cycle

Symbolic model checking: 10 20 States and beyond

Probabilistic state space search

Methods for exploiting SAT solvers in unbounded model checking

Sequential circuit verification using symbolic model checking

Engineering change in a non-deterministic FSM setting

Fast discrete function evaluation using decision diagrams

Algorithms for interface timing verification

Symbolic model checking: 10/sup 20/ states and beyond

Patterns of NPP, GPP, respiration, and NEP during boreal forest succession

Development and Validation of a Kinetic Model for Enzymatic Saccharification of Lignocellulosic Biomass

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