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Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Applied physics express, 2008-09, Vol.1, p.91301

2008

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Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

Journal of applied physics, 2012-04, Vol.111 (7), p.07E336-07E336-3

2012

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High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism

IEEE transactions on circuits and systems. I, Regular papers, 2014-03, Vol.61 (3), p.865-876

2014

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Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Japanese Journal of Applied Physics, 2012-02, Vol.51 (2), p.02BM06-02BM06-5

2012

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Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices

Applied physics express, 2009-02, Vol.2, p.23004

2009

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Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

Japanese Journal of Applied Physics, 2011-06, Vol.50 (6), p.063004-063004-7

2011

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High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012, p.41-48

2012

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Fine-Grained Power-Gating Scheme of a Metal--Oxide--Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.04DM05-04DM05-5

2010

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Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Japanese Journal of Applied Physics, 2012-02, Vol.51 (2S), p.2

2012

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A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014, p.1-8

2014

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Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme

IEICE Electronics Express, 2014-01, Vol.11 (3), p.20131006-20131006

2014

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Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015, p.1006-1011

2015

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Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.1006-1011

2015

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MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.433-435

2009

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Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme

IEICE Electronics Express, 2014, Vol.11 (10), p.20140297-20140297

2014

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High-throughput CAM based on a synchronous overlapped search scheme

IEICE Electronics Express, 2013-01, Vol.10 (7), p.20130148-20130148

2013

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Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM

2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 2012, p.98-103

2012

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Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme

2011 41st IEEE International Symposium on Multiple-Valued Logic, 2011, p.99-104

2011

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Soft-Delay-Error Evaluation in Content-Addressable Memory

2014 IEEE 44th International Symposium on Multiple-Valued Logic, 2014, p.220-225

2014

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Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

Japanese Journal of Applied Physics, 2011-06, Vol.50 (6R), p.63004

2011

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Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014, p.193-196

2014

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Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction

10th IEEE International NEWCAS Conference, 2012, p.485-488

2012

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MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

Proceedings of the Conference on Design, Automation and Test in Europe, 2009, p.433-435

2009

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Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices

Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

Fine-Grained Power-Gating Scheme of a Metal--Oxide--Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme

High-throughput CAM based on a synchronous overlapped search scheme

Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM

Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme

Soft-Delay-Error Evaluation in Content-Addressable Memory

Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

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