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A compact model for tunnel field-effect transistors incorporating nonlocal band-to-band tunneling

Journal of applied physics, 2013-10, Vol.114 (14)

2013

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Demonstration, analysis, and device design considerations for independent DG MOSFETs

IEEE transactions on electron devices, 2005-09, Vol.52 (9), p.2046-2053

2005

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Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

IEEE electron device letters, 2003-07, Vol.24 (7), p.484-486

2003

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Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

IEEE transactions on nanotechnology, 2006-11, Vol.5 (6), p.723-730

2006

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A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

IEEE electron device letters, 2004-07, Vol.25 (7), p.510-512

2004

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Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

Solid-state electronics, 2015-09, Vol.111, p.62-66

2015

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Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.2078-2085

2004

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Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

IEEE electron device letters, 2009-07, Vol.30 (7), p.757-759

2009

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Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

IEEE transactions on electron devices, 2006-08, Vol.53 (8), p.1826-1833

2006

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Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

IEEE electron device letters, 2007-12, Vol.28 (12), p.1123-1125

2007

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Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness

IEEE electron device letters, 2009-04, Vol.30 (4), p.407-409

2009

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Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch

Optics express, 2013-03, Vol.21 (6), p.6889-6894

2013

Volltextzugriff (PDF)

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

IEEE electron device letters, 2009-05, Vol.30 (5), p.556-558

2009

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Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

IEEE transactions on electron devices, 2008-09, Vol.55 (9), p.2454-2461

2008

Volltextzugriff (PDF)

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

IEEE electron device letters, 2007-03, Vol.28 (3), p.217-219

2007

Volltextzugriff (PDF)

A Ta/Mo Interdiffusion Dual Metal Gate Technology for Drivability Enhancement of FinFETs

IEEE electron device letters, 2008-06, Vol.29 (6), p.618-620

2008

Volltextzugriff (PDF)

On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs

2010 Symposium on VLSI Technology, 2010, p.101-102

2010

Volltextzugriff (PDF)

Impact of atomic-scale structural design on ultra-short channel (3 nm) MOSFETs

2013 IEEE 5th International Nanoelectronics Conference (INEC), 2013, p.132-135

2013

Volltextzugriff (PDF)

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1431-1437

2007

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A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate FinFETs

IEEE electron device letters, 2007-05, Vol.28 (5), p.452-454

2007

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Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

IEEE transactions on nanotechnology, 2003-12, Vol.2 (4), p.198-204

2003

Volltextzugriff (PDF)

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration

2014 44th European Solid State Device Research Conference (ESSDERC), 2014, p.278-281

2014

Volltextzugriff (PDF)

Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation

IEEE transactions on nanotechnology, 2007-03, Vol.6 (2), p.201-205

2007

Volltextzugriff (PDF)

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013, p.45-48

2013

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Analysis of Vth flexibility in ultrathin-BOX SOI FinFETs

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

Volltextzugriff (PDF)

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A compact model for tunnel field-effect transistors incorporating nonlocal band-to-band tunneling

Demonstration, analysis, and device design considerations for independent DG MOSFETs

Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

A Ta/Mo Interdiffusion Dual Metal Gate Technology for Drivability Enhancement of FinFETs

On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs

Impact of atomic-scale structural design on ultra-short channel (3 nm) MOSFETs

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate FinFETs

Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration

Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

Analysis of Vth flexibility in ultrathin-BOX SOI FinFETs

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