UB Paderborn / Katalog / Suche / in CDI

A comparison of quantitative EEG features for neonatal seizure detection

Clinical neurophysiology, 2008-06, Vol.119 (6), p.1248-1261

2008

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Network-on-Chip interconnect for pairing-based cryptographic IP cores

Journal of systems architecture, 2011, Vol.57 (1), p.95-108

2011

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Hardware Implementation of (2^) LDPC Decoders

IEEE transactions on circuits and systems. I, Regular papers, 2009-12, Vol.56 (12), p.2609-2620

2009

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Versatile processor for GF(pm) arithmetic for use in cryptographic applications

IET computers & digital techniques, 2008-07, Vol.2 (4), p.253-253

2008

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A hardware wrapper for the SHA-3 hash algorithms

IET Irish Signals and Systems Conference (ISSC 2010), 2010, p.1-6

2010

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Energy-Efficient Low Duty Cycle MAC Protocol for Wireless Body Area Networks

IEEE transactions on information technology in biomedicine, 2009-11, Vol.13 (6), p.915-925

2009

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A Gaussian mixture model based statistical classification system for neonatal seizure detection

2009 IEEE International Workshop on Machine Learning for Signal Processing, 2009, p.1-6

2009

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An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005, 2005, Vol.3, p.1412-1418 Vol. 3

2005

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Versatile hardware architectures for GF ( p m ) arithmetic in public key cryptography

Integration (Amsterdam), 2007, Vol.40 (1), p.28-35

2007

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Optimised bit serial modular multiplier for implementation on field programmable gate arrays

Electronics letters, 1998-04, Vol.34 (8), p.738

Marnane, W.P.

1998

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Bit-serial interleaved high speed division

Electronics letters, 1997-06, Vol.33 (13), p.1124

1997

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Optimisation of the SHA-2 family of hash functions on FPGAs

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006, p.6 pp.

2006

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FPGA Implementation of an Elliptic Curve Processor Using the GLV Method

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.249-254

2009

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High-performance computing for real-time spectral estimation

Control engineering practice, 1999-05, Vol.7 (5), p.679-686

1999

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Versatile Processor for GF(pm) Arithmetic for use in Cryptographic Applications

2006 NORCHIP, 2006, p.281-284

2006

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Automated single channel seizure detection in the neonate

2008 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2008-01, Vol.2008, p.915-918

2008

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Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.255-260

2009

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A low-power wireless ECG processing node and remote monitoring system

IET Irish Signals and Systems Conference (ISSC 2010), 2010, p.48-53

2010

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Area-Efficient Processor for Public-Key Cryptography in Wireless Sensor Networks

2008 Second International Conference on Sensor Technologies and Applications (sensorcomm 2008), 2008, p.667-672

2008

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Seizure detection in neonates: Improved classification through supervised adaptation

2008 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2008-01, Vol.2008, p.903-906

2008

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Reducing routing congestion in a cryptographic IP core using NoC interconnect

IET Irish Signals and Systems Conference (ISSC 2010), 2010, p.210-215

2010

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A comparison of generative and discriminative approaches in automated neonatal seizure detection

2009 IEEE International Symposium on Intelligent Signal Processing, 2009, p.181-186

2009

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FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, p.783-790

2009

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Side channel analysis of an automotive microprocessor

IET Irish Signals and Systems Conference (ISSC 2008), 2008, p.4-9

2008

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Efficient Real-Time Correlator for LS Sequences

2007 IEEE International Symposium on Industrial Electronics, 2007, p.1663-1668

2007

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A comparison of quantitative EEG features for neonatal seizure detection

Network-on-Chip interconnect for pairing-based cryptographic IP cores

Hardware Implementation of (2^) LDPC Decoders

Versatile processor for GF(pm) arithmetic for use in cryptographic applications

A hardware wrapper for the SHA-3 hash algorithms

Energy-Efficient Low Duty Cycle MAC Protocol for Wireless Body Area Networks

A Gaussian mixture model based statistical classification system for neonatal seizure detection

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Versatile hardware architectures for GF ( p m ) arithmetic in public key cryptography

Optimised bit serial modular multiplier for implementation on field programmable gate arrays

Bit-serial interleaved high speed division

Optimisation of the SHA-2 family of hash functions on FPGAs

FPGA Implementation of an Elliptic Curve Processor Using the GLV Method

High-performance computing for real-time spectral estimation

Versatile Processor for GF(pm) Arithmetic for use in Cryptographic Applications

Automated single channel seizure detection in the neonate

Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC

A low-power wireless ECG processing node and remote monitoring system

Area-Efficient Processor for Public-Key Cryptography in Wireless Sensor Networks

Seizure detection in neonates: Improved classification through supervised adaptation

Reducing routing congestion in a cryptographic IP core using NoC interconnect

A comparison of generative and discriminative approaches in automated neonatal seizure detection

FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash

Side channel analysis of an automotive microprocessor

Efficient Real-Time Correlator for LS Sequences

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