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Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-08, Vol.36 (8), p.1381-1394

2017

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FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-02, Vol.30 (2), p.194-204

2011

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Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-02, Vol.35 (2), p.246-259

2016

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Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-07, Vol.36 (7), p.1103-1112

2017

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Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-10, Vol.34 (10), p.1652-1663

2015

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Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement

IEEE transactions on very large scale integration (VLSI) systems, 2013-03, Vol.21 (3), p.523-532

2013

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E-Beam Lithography Character and Stencil Co-Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-05, Vol.33 (5), p.741-751

2014

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Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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Efficient Qubit Routing Using a Dynamically-Extract-and-Route Framework

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

2024

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Rethinking the Wirelength Benefit of 3-D Integration

IEEE transactions on very large scale integration (VLSI) systems, 2012-12, Vol.20 (12), p.2346-2351

2012

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Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1255-1267

2023

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Power-Driven Flip-Flop Merging and Relocation

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-02, Vol.31 (2), p.180-191

2012

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IEEE_Xplore

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-12, Vol.32 (12), p.1866-1878

2013

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IEEE_Xplore

Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-03, Vol.37 (3), p.657-668

2018

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IEEE_Xplore

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-03, Vol.40 (3), p.494-506

2021

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IEEE_Xplore

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-07, Vol.30 (7), p.1020-1033

2011

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A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

IEEE transactions on applied superconductivity, 2022-08, Vol.32 (5), p.1-12

2022

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Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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IEEE_Xplore

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-10, Vol.32 (10), p.1557-1568

2013

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IEEE_Xplore

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-11, Vol.34 (11), p.1822-1835

2015

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IEEE_Xplore

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.1134-1139

2012

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IEEE_Xplore

Pad Assignment for Die-Stacking System-in-Package Design

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-11, Vol.31 (11), p.1711-1722

2012

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IEEE_Xplore

Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, p.1-9

2022

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IEEE_Xplore

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, p.1-9

2022

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IEEE_Xplore

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Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment

FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement

E-Beam Lithography Character and Stencil Co-Optimization

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

Efficient Qubit Routing Using a Dynamically-Extract-and-Route Framework

Rethinking the Wirelength Benefit of 3-D Integration

Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization

Power-Driven Flip-Flop Merging and Relocation

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules

Pad Assignment for Die-Stacking System-in-Package Design

Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization

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