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Sequential Element Design With Built-In Soft Error Resilience

IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1368-1378

2006

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Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1621-1633

2012

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First nosocomial cluster of COVID-19 due to the Delta variant in a major acute care hospital in Singapore: investigations and outbreak response

The Journal of hospital infection, 2022-04, Vol.122, p.27-34

2022

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Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2322-2325

2011

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Influenza vaccine failure in the tropics: a retrospective cohort study of waning effectiveness

Epidemiology and infection, 2020-12, Vol.148, p.e299, Article e299

2020

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3D Simulations of the Archean Earth Including Photochemical Haze Profiles

Journal of geophysical research. Atmospheres, 2023-10, Vol.128 (20)

2023

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Implications of clock distribution faults and issues with screening them during manufacturing testing

IEEE transactions on computers, 2004-05, Vol.53 (5), p.531-546

2004

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New Design for Testability Approach for Clock Fault Testing

IEEE transactions on computers, 2012-04, Vol.61 (4), p.448-457

2012

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Low-Cost On-Chip Clock Jitter Measurement Scheme

IEEE transactions on very large scale integration (VLSI) systems, 2015-03, Vol.23 (3), p.435-443

2015

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Interposer test: Testing PCBs that have shrunk 100x

2014 International Test Conference, 2014, p.1-1

Mak, TM

2014

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Trends in manufacturing test methods and their implications

2004 International Conferce on Test, 2004, p.679-687

2004

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Clock Faults Induced Min and Max Delay Violations

Journal of electronic testing, 2014-02, Vol.30 (1), p.111-123

2014

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Innovative practices session 3C: Solving today's test challenges

2014 IEEE 32nd VLSI Test Symposium (VTS), 2014, p.1-1

2014

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Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

IEEE transactions on computers, 2007-03, Vol.56 (3), p.415-428

2007

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Built-In Soft Error Resilience for Robust System Design

2007 IEEE International Conference on Integrated Circuit Design and Technology, 2007, p.1-6

2007

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On path-based learning and its applications in delay test and diagnosis

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.492-497

2004

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Testing and Diagnosing High-Speed Circuits for Military Applications Through Standard Input/Output Ports

2023 IEEE AUTOTESTCON, 2023, p.1-8

2023

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Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003, p.668-673

2003

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Risks associated with faults within test pattern compactors and their implications on testing

2004 International Conferce on Test, 2004, p.1223-1231

2004

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Do we need anything more than single bit error correction (ECC)?

Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004, 2004, p.111-116

2004

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A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources

ACM transactions on design automation of electronic systems, 2018-01, Vol.23 (1), p.1-21

2018

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Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, 2009, p.191-196

2009

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New challenges in delay testing of nanometer, multigigahertz designs

IEEE design & test of computers, 2004-05, Vol.21 (3), p.241-248

2004

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Defect and error tolerance in the presence of massive numbers of defects

IEEE design & test of computers, 2004-05, Vol.21 (3), p.216-227

2004

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Is System in Package the Panacea for Integration?

IEEE design & test of computers, 2006-05, Vol.23 (3), p.256-256

Mak, T.M.

2006

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Sequential Element Design With Built-In Soft Error Resilience

Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint

First nosocomial cluster of COVID-19 due to the Delta variant in a major acute care hospital in Singapore: investigations and outbreak response

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

Influenza vaccine failure in the tropics: a retrospective cohort study of waning effectiveness

3D Simulations of the Archean Earth Including Photochemical Haze Profiles

Implications of clock distribution faults and issues with screening them during manufacturing testing

New Design for Testability Approach for Clock Fault Testing

Low-Cost On-Chip Clock Jitter Measurement Scheme

Interposer test: Testing PCBs that have shrunk 100x

Trends in manufacturing test methods and their implications

Clock Faults Induced Min and Max Delay Violations

Innovative practices session 3C: Solving today's test challenges

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

Built-In Soft Error Resilience for Robust System Design

On path-based learning and its applications in delay test and diagnosis

Testing and Diagnosing High-Speed Circuits for Military Applications Through Standard Input/Output Ports

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Risks associated with faults within test pattern compactors and their implications on testing

Do we need anything more than single bit error correction (ECC)?

A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

New challenges in delay testing of nanometer, multigigahertz designs

Defect and error tolerance in the presence of massive numbers of defects

Is System in Package the Panacea for Integration?

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