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Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications

2007 IEEE 13th International Symposium on High Performance Computer Architecture, 2007, p.25-36

2007

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Trimaran: An Infrastructure for Research in Instruction-Level Parallelism

Languages and Compilers for High Performance Computing, 2005, Vol.3602, p.32-41

2005

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Compiler-directed Data Partitioning for Multicluster Processors

Code Generation and Optimization: Proceedings of the International Symposium on Code Generation and Optimization; 26-29 Mar. 2006, 2006, p.208-220

2006

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Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008, p.166-176

2008

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Automated custom instruction generation for domain-specific processor acceleration

IEEE transactions on computers, 2005-10, Vol.54 (10), p.1258-1270

2005

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Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache

Code Generation and Optimization: Proceedings of the international symposium on Code generation and optimization; 20-23 Mar. 2005, 2005, p.179-190

2005

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Automatic and efficient evaluation of memory hierarchies for embedded systems

MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.114-125

1999

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Cost-sensitive partitioning in an architecture synthesis system for multicluster processors

IEEE MICRO, 2004-05, Vol.24 (3), p.10-20

2004

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Encore: low-cost, fine-grained transient fault recovery

2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011, p.398-409

2011

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Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

ACM transactions on design automation of electronic systems, 2000-10, Vol.5 (4), p.752-773

2000

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Compiler technology for future microprocessors

Proceedings of the IEEE, 1995-12, Vol.83 (12), p.1625-1640

1995

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The importance of prepass code scheduling for superscalar and superpipelined processors

IEEE transactions on computers, 1995-03, Vol.44 (3), p.353-370

1995

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Code and data partitioning for fine-grain parallelism

ACM SIGPLAN/SIGBED 2007 Conference on Languages, Compilers, and for Embedded Systems (LCTES '07); San Diego, CA; USA; 13-15 June 2007, 2007-07, Vol.42 (7), p.161-164

2007

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The partial reverse if-conversion framework for balancing control flow and predication

International journal of parallel programming, 1999-10, Vol.27 (5), p.381-423

1999

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Partitioning variables across register windows to reduce spill code in a low-power processor

IEEE transactions on computers, 2005-08, Vol.54 (8), p.998-1012

2005

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Code and data partitioning for fine-grain parallelism

Language, Compiler and Tool Support for Embedded Systems: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools; 13-15 June 2007, 2007, p.161-164

2007

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Profile-assisted instruction scheduling

International journal of parallel programming, 1994-04, Vol.22 (2), p.151-181

1994

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Dynamic memory disambiguation using the memory conflict buffer

ASPLOS-VI proceedings, 1994-12, Vol.28 (5), p.183-193

1994

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IMPACT:an architectural framework for multiple-instruction-issue processors

International Symposium on Computer Architecture: 25 years of the international symposia on Computer architecture (selected papers); 27 June-02 July 1998, 1998, p.408-417

1998

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The superblock: An effective technique for VLIW and superscalar compilation

The Journal of supercomputing, 1993-05, Vol.7 (1-2), p.229-248

1993

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Data access microarchitectures for superscalar processors with compiler-assisted data prefetching

International Symposium on Microarchitecture: Proceedings of the 24th annual international symposium on Microarchitecture, 1991, p.69-73

1991

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Comparing static and dynamic code scheduling for multiple-instruction-issue processors

International Symposium on Microarchitecture: Proceedings of the 24th annual international symposium on Microarchitecture, 1991, p.25-33

1991

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Using profile information to assist classic code optimizations

Software, practice & experience, 1991-12, Vol.21 (12), p.1301-1321

1991

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Increasing the number of effective registers in a low-power processor using a windowed register file

International Conference on Compilers, Architecture and Synthesis for Embedded Systems: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems; 30 Oct.-01 Nov. 2003, 2003, p.125-136

2003

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Automatic speculative DOALL for clusters

Proceedings of the Tenth International Symposium on Code Generation and Optimization, 2012, p.94-103

2012

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Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications

Trimaran: An Infrastructure for Research in Instruction-Level Parallelism

Compiler-directed Data Partitioning for Multicluster Processors

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

Automated custom instruction generation for domain-specific processor acceleration

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache

Automatic and efficient evaluation of memory hierarchies for embedded systems

Cost-sensitive partitioning in an architecture synthesis system for multicluster processors

Encore: low-cost, fine-grained transient fault recovery

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

Compiler technology for future microprocessors

The importance of prepass code scheduling for superscalar and superpipelined processors

Code and data partitioning for fine-grain parallelism

The partial reverse if-conversion framework for balancing control flow and predication

Partitioning variables across register windows to reduce spill code in a low-power processor

Code and data partitioning for fine-grain parallelism

Profile-assisted instruction scheduling

Dynamic memory disambiguation using the memory conflict buffer

IMPACT:an architectural framework for multiple-instruction-issue processors

The superblock: An effective technique for VLIW and superscalar compilation

Data access microarchitectures for superscalar processors with compiler-assisted data prefetching

Comparing static and dynamic code scheduling for multiple-instruction-issue processors

Using profile information to assist classic code optimizations

Increasing the number of effective registers in a low-power processor using a windowed register file

Automatic speculative DOALL for clusters

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