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Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2719-2725

2011

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Impact of Technology Scaling on SRAM Soft Error Rates

IEEE transactions on nuclear science, 2014-12, Vol.61 (6), p.3512-3518

2014

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Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4200-4206

2013

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Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.457-463

2017

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Effects of Temperature and Supply Voltage on SEU- and SET-Induced Errors in Bulk 40-nm Sequential Circuits

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2122-2128

2017

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Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2613-2619

2015

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Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2761-2767

2011

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Geometry Dependence of Total-Dose Effects in Bulk FinFETs

IEEE transactions on nuclear science, 2014-12, Vol.61 (6), p.2951-2958

2014

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The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2440-2451

2015

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Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2098-2106

2017

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Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2796-2802

2012

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Effects of Total-Ionizing-Dose Irradiation on SEU- and SET-Induced Soft Errors in Bulk 40-nm Sequential Circuits

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.471-476

2017

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Analysis of Temporal Masking Effects on Master- and Slave-Type Flip-Flop SEUs and Related Applications

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1823-1829

2018

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Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty

IEEE transactions on nuclear science, 2013-08, Vol.60 (4), p.2776-2781

2013

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Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2966-2973

2012

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Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

IEEE transactions on nuclear science, 2016-02, Vol.63 (1), p.385-391

2016

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Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4394-4398

2013

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Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2592-2598

2015

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Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors

IEEE transactions on nuclear science, 2014-12, Vol.61 (6), p.3274-3281

2014

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Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4498-4504

2013

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Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies

2010 IEEE International Reliability Physics Symposium, 2010, p.1031-1035

2010

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Impact of Strained-Si PMOS Transistors on SRAM Soft Error Rates

IEEE transactions on nuclear science, 2012-08, Vol.59 (4), p.845-850

2012

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Estimating the frequency threshold for logic soft errors

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.3D.3.1-3D.3.6

2013

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A critical re-examination of body-bias on the soft error rate and single-event latch-up in automotive SRAMs

2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.2E-2.1-2E-2.5

2017

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An efficient technique to select logic nodes for single event transient pulse-width reduction

Microelectronics and reliability, 2013-01, Vol.53 (1), p.114-117

2013

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Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

Impact of Technology Scaling on SRAM Soft Error Rates

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes

Effects of Temperature and Supply Voltage on SEU- and SET-Induced Errors in Bulk 40-nm Sequential Circuits

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs

Geometry Dependence of Total-Dose Effects in Bulk FinFETs

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

Effects of Total-Ionizing-Dose Irradiation on SEU- and SET-Induced Soft Errors in Bulk 40-nm Sequential Circuits

Analysis of Temporal Masking Effects on Master- and Slave-Type Flip-Flop SEUs and Related Applications

Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty

Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes

Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits

Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies

Impact of Strained-Si PMOS Transistors on SRAM Soft Error Rates

Estimating the frequency threshold for logic soft errors

A critical re-examination of body-bias on the soft error rate and single-event latch-up in automotive SRAMs

An efficient technique to select logic nodes for single event transient pulse-width reduction

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