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Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery

2022 IEEE International Reliability Physics Symposium (IRPS), 2022, p.1-6

2022

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Analysis of silicon germanium vapor phase epitaxy kinetics

Thin solid films, 2010, Vol.518 (6), p.S12-S17

2010

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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T142-T143

2015

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Phase formation and texture of nickel silicides on Si1―xCx epilayers

Microelectronic engineering, 2011-05, Vol.88 (5), p.536-540

2011

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Reliability Engineering Enabling Continued Logic for Memory Device Scaling

2019 IEEE International Integrated Reliability Workshop (IIRW), 2019, p.1-11

2019

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Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs

2019 IEEE International Integrated Reliability Workshop (IIRW), 2019, p.1-5

2019

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Holistic technology optimization and key enablers for 7nm mobile SoC

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T198-T199

2015

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Stability of silicon germanium stressors

Thin solid films, 2010, Vol.518 (6), p.S133-S135

2010

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Improved thermal stability of Ni-silicides on Si:C epitaxial layers

Microelectronic engineering, 2007-11, Vol.84 (11), p.2542-2546

2007

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Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

IEEE transactions on electron devices, 2008-03, Vol.55 (3), p.925-930

2008

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A power rate law study of silicon germanium selective vapor phase epitaxy kinetics

Materials science in semiconductor processing, 2009-06, Vol.12 (3), p.126-131

2009

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Low temperature epitaxy and the importance of moisture control

Thin solid films, 2008-11, Vol.517 (1), p.416-418

2008

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Electrical demonstration of thermally stable Ni silicides on Si1-xCx epitaxial layers

Microelectronic engineering, 2010-03, Vol.87 (3), p.306-310

2010

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Stress analysis of Si1-xGex embedded source/drain junctions

Materials science in semiconductor processing, 2008-10, Vol.11 (5-6), p.285-290

2008

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Leakage current study of Si1-xCx embedded source/drain junctions

Applied surface science, 2008-07, Vol.254 (19), p.6140-6143

2008

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DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.306-307

2022

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Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications

2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.DG-8.1-DG-8.5

2017

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Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices

2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-8

2019

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Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs

2017 International Conference on Noise and Fluctuations (ICNF), 2017, p.1-4

2017

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Tensile Strained Selective Silicon Carbon Alloys for Recessed Source Drain Areas of Devices

ECS transactions, 2006, Vol.3 (7), p.187-196

2006

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Holistic technology optimization and key enablers for 7nm mobile SoC

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.T198-T199

2015

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High Efficiency Low Temperature Pre-epi Clean Method for Advanced Group IV epi Processing

ECS transactions, 2013, Vol.50 (9), p.339-348

2013

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Extrinsic magnetoresistance in bulk sintered manganites

Journal of magnetism and magnetic materials, 1999-05, Vol.196, p.461-462

1999

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Phase formation and texture of nickel silicides on Si sub(1-) sub(x)C sub(x epilayers)

Microelectronic engineering, 2011-05, Vol.88 (5), p.536-540

2011

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Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery

Analysis of silicon germanium vapor phase epitaxy kinetics

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Phase formation and texture of nickel silicides on Si1―xCx epilayers

Reliability Engineering Enabling Continued Logic for Memory Device Scaling

Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs

Holistic technology optimization and key enablers for 7nm mobile SoC

Stability of silicon germanium stressors

Improved thermal stability of Ni-silicides on Si:C epitaxial layers

Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

A power rate law study of silicon germanium selective vapor phase epitaxy kinetics

Low temperature epitaxy and the importance of moisture control

Electrical demonstration of thermally stable Ni silicides on Si1-xCx epitaxial layers

Stress analysis of Si1-xGex embedded source/drain junctions

Leakage current study of Si1-xCx embedded source/drain junctions

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories

Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices

Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs

Tensile Strained Selective Silicon Carbon Alloys for Recessed Source Drain Areas of Devices

Holistic technology optimization and key enablers for 7nm mobile SoC

High Efficiency Low Temperature Pre-epi Clean Method for Advanced Group IV epi Processing

Extrinsic magnetoresistance in bulk sintered manganites

Phase formation and texture of nickel silicides on Si sub(1-) sub(x)C sub(x epilayers)

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