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A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.670-675

2022

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Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Transactions on Computational Science IV, p.230-243

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Cryptanalysis of AES and Camellia with Related S-boxes

Progress in Cryptology – AFRICACRYPT 2013, p.208-221

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Efficient software implementation of AES on 32-bit platforms

Lecture notes in computer science, 2002, p.159-171

2002

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Efficient Software Implementation of AES on 32-Bit Platforms

Cryptographic Hardware and Embedded Systems - CHES 2002, p.159-171

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A New Fast and Side-Channel Resistant AES Hardware Architecture

2023 IEEE International Conference on Cyber Security and Resilience (CSR), 2023, p.572-579

2023

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Revisiting the IDEA Philosophy

Fast Software Encryption, p.277-295

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A Complete Formulation of Generalized Affine Equivalence

Lecture notes in computer science, 2005, p.338-347

2005

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The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.3, p.70-75 Vol.3

2004

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ASIC hardware implementation of the IDEA NXT encryption algorithm

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-4846

2006

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Progress in Cryptology - AFRICACRYPT 2013: 6th International Conference on Cryptology in Africa, Cairo, Egypt, June 22-24, 2013, Proceedings

2013, 2013

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On the Generalized Linear Equivalence of Functions Over Finite Fields

Advances in Cryptology - ASIACRYPT 2004, 2004, p.79-91

2004

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Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.731-737

2007

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Evaluating physically unclonable functions on a large set of FPGAs

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016, p.188-195

2016

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Efficient AES implementations for ARM based platforms

Proceedings of the 2004 ACM symposium on Applied computing, 2004, p.841-845

2004

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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

Great Lakes Symposium on VLSI: Proceedings of the 14th ACM Great Lakes symposium on VLSI; 26-28 Apr. 2004, 2004, p.421-425

2004

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Power-efficient ASIC synthesis of cryptographic sboxes

Great Lakes Symposium on VLSI: Proceedings of the 14th ACM Great Lakes symposium on VLSI; 26-28 Apr. 2004, 2004, p.277-281

2004

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A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2007, p.209-214

2007

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The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)

Proceedings of the conference on Design, automation and test in Europe - Volume 3, 2004, p.30070-30070

2004

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A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Cryptanalysis of AES and Camellia with Related S-boxes

Efficient software implementation of AES on 32-bit platforms

Efficient Software Implementation of AES on 32-Bit Platforms

A New Fast and Side-Channel Resistant AES Hardware Architecture

Revisiting the IDEA Philosophy

A Complete Formulation of Generalized Affine Equivalence

The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)

ASIC hardware implementation of the IDEA NXT encryption algorithm

Progress in Cryptology - AFRICACRYPT 2013: 6th International Conference on Cryptology in Africa, Cairo, Egypt, June 22-24, 2013, Proceedings

On the Generalized Linear Equivalence of Functions Over Finite Fields

Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes

Evaluating physically unclonable functions on a large set of FPGAs

Efficient AES implementations for ARM based platforms

An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

Power-efficient ASIC synthesis of cryptographic sboxes

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)

Linguistic profile automated characterisation in pluripotential clinical high-risk mental state (CHARMS) conditions: methodology of a multicentre observational study

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