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An analytical model for designing memory hierarchies

IEEE transactions on computers, 1996-10, Vol.45 (10), p.1180-1194

1996

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A semi-Markov model for the performance of multiple-bus systems

IEEE transactions on computers, 1985-10, Vol.C-34 (10), p.934-942

1985

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Multilevel optimization of pipelined caches

IEEE transactions on computers, 1997-10, Vol.46 (10), p.1093-1102

1997

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Recognizing Partially Occluded Parts

IEEE transactions on pattern analysis and machine intelligence, 1985-07, Vol.PAMI-7 (4), p.410-421

1985

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Analysis and design of latch-controlled synchronous digital circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-03, Vol.11 (3), p.322-333

1992

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Multiple Bus Architectures

Computer (Long Beach, Calif.), 1987-06, Vol.20 (6), p.42-48

1987

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Multilevel optimization in the design of a high-performance GaAs microcomputer

IEEE journal of solid-state circuits, 1991-05, Vol.26 (5), p.763-767

1991

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Synchronization of pipelines

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-08, Vol.12 (8), p.1132-1146, Article 1132

1993

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Gallium-arsenide process evaluation based on a RISC microprocessor example

IEEE journal of solid-state circuits, 1993-10, Vol.28 (10), p.1030-1037

1993

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Translation and execution of distributed Ada programs: Is it still Ada?

IEEE transactions on software engineering, 1989-03, Vol.15 (3), p.281-292

1989

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Automatic generation of salient features for the recognition of partially occluded parts

Robotica, 1987-04, Vol.5 (2), p.117-127

1987

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Hierarchical gate-array routing on a hypercube multiprocessor

Journal of parallel and distributed computing, 1990-04, Vol.8 (4), p.313-324

1990

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Object-Based Computing and the Ada Programming Language

Computer (Long Beach, Calif.), 1985-03, Vol.18 (3), p.11-19

1985

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Unifying Robot Arm Control

IEEE transactions on industry applications, 1984-11, Vol.IA-20 (6), p.1554-1563

1984

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Memory Interference Models with Variable Connection Time

IEEE transactions on computers, 1984-11, Vol.C-33 (11), p.1033-1038

1984

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A Class of Cellular Architectures to Support Physical Design Automation

IEEE transactions on computer-aided design of integrated circuits and systems, 1984-10, Vol.3 (4), p.264-278

1984

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Cache coherence requirements for interprocess rendezvous

International journal of parallel programming, 1990-02, Vol.19 (1), p.31-51

1990

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Critical paths in circuits with level-sensitive latches

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.273-291

1995

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Overview of complementary GaAs technology for high-speed VLSI circuits

IEEE transactions on very large scale integration (VLSI) systems, 1998-03, Vol.6 (1), p.47-51

1998

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Trace-driven memory simulation: a survey

ACM computing surveys, 1997-06, Vol.29 (2), p.128-170

1997

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Memory-interference model for multiprocessors based on semi-Markov processes

IEE proceedings. Part E, Computers and digital techniques, 1987-07, Vol.134 (4), p.203

1987

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A preliminary investigation into parallel routing on a hypercube computer

24th ACM/IEEE Design Automation Conference, 1987, p.814-820

1987

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Using Ada as a programming language for robot-based manufacturing cells

IEEE transactions on systems, man, and cybernetics, 1984-11, Vol.SMC-14 (6), p.863-878

1984

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Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique

The International journal of robotics research, 1989-12, Vol.8 (6), p.110-131

1989

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Solutions to the n Queens problem using tasking in Ada

SIGPLAN notices, 1986-12, Vol.21 (12), p.99-110

1986

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An analytical model for designing memory hierarchies

A semi-Markov model for the performance of multiple-bus systems

Multilevel optimization of pipelined caches

Recognizing Partially Occluded Parts

Analysis and design of latch-controlled synchronous digital circuits

Multiple Bus Architectures

Multilevel optimization in the design of a high-performance GaAs microcomputer

Synchronization of pipelines

Gallium-arsenide process evaluation based on a RISC microprocessor example

Translation and execution of distributed Ada programs: Is it still Ada?

Automatic generation of salient features for the recognition of partially occluded parts

Hierarchical gate-array routing on a hypercube multiprocessor

Object-Based Computing and the Ada Programming Language

Unifying Robot Arm Control

Memory Interference Models with Variable Connection Time

A Class of Cellular Architectures to Support Physical Design Automation

Cache coherence requirements for interprocess rendezvous

Critical paths in circuits with level-sensitive latches

Overview of complementary GaAs technology for high-speed VLSI circuits

Trace-driven memory simulation: a survey

Memory-interference model for multiprocessors based on semi-Markov processes

A preliminary investigation into parallel routing on a hypercube computer

Using Ada as a programming language for robot-based manufacturing cells

Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique

Solutions to the n Queens problem using tasking in Ada

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