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SCFIT: A FPGA-based fault injection technique for SEU fault model

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.586-589

2012

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A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems

Dependable Computing, 2005, p.143-153

2005

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Crosstalk modeling to predict channel delay in Network-on-Chips

2010 IEEE International Conference on Computer Design, 2010, p.396-401

2010

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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

IET computers & digital techniques, 2009, Vol.3 (3), p.289-303

2009

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Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

IEEE transactions on very large scale integration (VLSI) systems, 2006-04, Vol.14 (4), p.323-335

2006

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Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007, p.276-285

2007

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An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors

2009 IEEE/IFIP International Conference on Dependable Systems & Networks, 2009, p.195-204

2009

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ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

2011 Design, Automation & Test in Europe, 2011, p.1-4

2011

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A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, p.193-201

2008

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FPGA-based Monte Carlo simulation for fault tree analysis

Microelectronics and reliability, 2004-06, Vol.44 (6), p.1017-1028

2004

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FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips

2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing, 2010, p.55-61

2010

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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies1

IET computers & digital techniques, 2009-05, Vol.3 (3), p.289-289

2009

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A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design

2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN), 2010, p.131-140

2010

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CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing

Microelectronics and reliability, 2006-05, Vol.46 (5), p.959-972

2006

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A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors

2008 11th IEEE High Assurance Systems Engineering Symposium, 2008, p.109-116

2008

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Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

2011 Design, Automation & Test in Europe, 2011, p.1-6

2011

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Transient detection in COTS processors using software approach

Microelectronics and reliability, 2006, Vol.46 (1), p.124-133

2006

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Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme

Dependable Computing, 2005, p.121-130

2005

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A fault-tolerant cache architecture based on binary set partitioning

Microelectronics and reliability, 2006, Vol.46 (1), p.86-99

2006

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Switch Level Fault Emulation

Field Programmable Logic and Application, 2003, p.849-858

2003

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FPGA-based fault injection into switch-level models

Microprocessors and microsystems, 2004-08, Vol.28 (5), p.317-327

2004

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A Highly Fault Detectable Cache Architecture for Dependable Computing

Computer Safety, Reliability, and Security, 2004, p.45-59

2004

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An efficient technique to tolerate MBU faults in register file of embedded processors

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012, p.115-120

2012

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Dependability analysis using a fault injection tool based on synthesizability of HDL models

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, p.485-492

2003

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Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features

Journal of electronic testing, 2004-10, Vol.20 (5), p.553-567

2004

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SCFIT: A FPGA-based fault injection technique for SEU fault model

A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems

Crosstalk modeling to predict channel delay in Network-on-Chips

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies

An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors

ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs

FPGA-based Monte Carlo simulation for fault tree analysis

FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies1

A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design

CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing

A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

Transient detection in COTS processors using software approach

Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme

A fault-tolerant cache architecture based on binary set partitioning

Switch Level Fault Emulation

FPGA-based fault injection into switch-level models

A Highly Fault Detectable Cache Architecture for Dependable Computing

An efficient technique to tolerate MBU faults in register file of embedded processors

Dependability analysis using a fault injection tool based on synthesizability of HDL models

Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features

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