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A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

IEEE transactions on electron devices, 2024-02, Vol.71 (2), p.1-6

2024

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A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

IEEE transactions on electron devices, 2021-05, Vol.68 (5), p.2265-2270

2021

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An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

IEEE access, 2024-01, Vol.12, p.1-1

2024

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Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

IEEE access, 2023, Vol.11, p.123577-123588

2023

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

IEEE access, 2021, Vol.9, p.108119-108130

2021

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An Approximate Low-Power Lifting Scheme Using Reversible Logic

IEEE access, 2020, Vol.8, p.183367-183377

2020

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Design of Approximate Booth Squarer for Error-Tolerant Computing

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1230-1241

2020

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A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2918-2922

2020

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A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications

IEEE transactions on circuits and systems. II, Express briefs, 2021-06, Vol.68 (6), p.1748-1752

2021

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A novel tunable bandgap voltage and current reference generation circuit

Analog integrated circuits and signal processing, 2021-05, Vol.107 (2), p.331-338

2021

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0.5 V, 254 μW Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

Circuits, systems, and signal processing, 2021-05, Vol.40 (5), p.2114-2134

2021

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Generation of complex impedance for complex filter design using fully balanced current conveyors

Analog integrated circuits and signal processing, 2020-11, Vol.105 (2), p.203-214

2020

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A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023, p.1-6

2023

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On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.3428-3432

2022

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Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications

SN computer science, 2020-11, Vol.1 (6), p.310, Article 310

2020

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Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications

Integration (Amsterdam), 2021-11, Vol.81, p.268-279

2021

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A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, p.19-24

2021

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Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, p.202-206

2016

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Design and analysis of multiplier using approximate 4-2 compressor

International journal of electronics and communications, 2019-07, Vol.107, p.89-97

2019

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Approximate Three-Operand Binary Adder for Error-Resilient Applications

2023 IEEE International Symposium on Smart Electronic Systems (iSES), 2023, p.287-291

2023

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pm \, 0.5$$ V, 254 $$\upmu $$W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

Circuits, systems, and signal processing, 2021-05, Vol.40 (5), p.2114-2134

2021

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36 μW fourth order sigma-delta modulator using single operational amplifier

International journal of electronics letters, 2021-04, Vol.9 (2), p.171-186

2021

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A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm

2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, p.127-130

2021

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Reversible Logic Implementation of Image Denoising for Grayscale Images

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.138-141

2020

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A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS

A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

An Approximate Low-Power Lifting Scheme Using Reversible Logic

Design of Approximate Booth Squarer for Error-Tolerant Computing

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications

A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications

A novel tunable bandgap voltage and current reference generation circuit

0.5 V, 254 μW Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

Generation of complex impedance for complex filter design using fully balanced current conveyors

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications

Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications

A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications

Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell

Design and analysis of multiplier using approximate 4-2 compressor

Approximate Three-Operand Binary Adder for Error-Resilient Applications

pm \, 0.5$$ V, 254 $$\upmu $$W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit

36 μW fourth order sigma-delta modulator using single operational amplifier

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS

Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm

Reversible Logic Implementation of Image Denoising for Grayscale Images

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