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Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics

Nature nanotechnology, 2013-03, Vol.8 (3), p.180-186

2013

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Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Frontiers in nanotechnology, 2022-01, Vol.3

2022

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Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.474-480

2020

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FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard

Yogesh Singh Chauhan, Darsen Duane Lu, Sriramkumar Venugopalan, Sourabh Khandelwal, Juan Pablo Duarte, Navid Paydavosi, Ai Niknejad, Chenming Hu

1, 2015

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Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack

Semiconductor science and technology, 2022-02, Vol.37 (2), p.24001

2022

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Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

IEEE electron device letters, 2021-08, Vol.42 (8), p.1144-1147

2021

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Bilayered Oxide Heterostructure‐Mediated Capacitance‐Based Neuroplasticity Modulation for Neuromorphic Classification

Advanced functional materials, 2023-12, Vol.33 (52), p.n/a

2023

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Impact of the Barrier Layer on the High Thermal and Mechanical Stability of a Flexible Resistive Memory in a Neural Network Application

ACS applied electronic materials, 2022-03, Vol.4 (3), p.1072-1081

2022

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Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering

ACS applied electronic materials, 2021-02, Vol.3 (2), p.619-628

2021

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Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

IEEE transactions on electron devices, 2019-06, Vol.66 (6), p.2509-2512

2019

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Performance-Aware Corner Model for Design for Manufacturing

IEEE transactions on electron devices, 2009-04, Vol.56 (4), p.595-600

2009

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BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

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BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations

Solid-state electronics, 2012, Vol.67 (1), p.79-89

2012

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Modeling Advanced FET Technology in a Compact Model

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.1971-1978

2006

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A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

Solid-state electronics, 2011-08, Vol.62 (1), p.31-39

2011

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A Novel Three-Dimensional 6T-SRAM Cell Featuring Vertical Transistors and 24F2 Layout Area

2021 7th International Conference on Applied System Innovation (ICASI), 2021, p.88-90

2021

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TCAD-Based RF performance prediction and process optimization of 3D monolithically stacked complementary FET

Solid-state electronics, 2023-03, Vol.201, p.108585, Article 108585

2023

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Automated extraction of barrier heights for asymmetric MIM tunneling diodes

Solid-state electronics, 2020-10, Vol.172, p.107879, Article 107879

2020

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First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.2101-2107

2022

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HfTaO x Rectifying Layer for HfO x ‑Based RRAM for High-Accuracy Neuromorphic Computing Applications

ACS applied electronic materials, 2023-05, Vol.5 (5), p.2566-2573

2023

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FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

IEEE electron device letters, 2017-01, Vol.38 (1), p.16-19

2017

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Global parameter extraction for a multi-gate MOSFETs compact model

2010 International Conference on Microelectronic Test Structures (ICMTS), 2010, p.194-197

2010

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Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, p.1-2

2021

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Computing-in-Memory with Ferroelectric Materials and Beyond

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-2

Lu, Darsen D.

2023

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An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

IEEE transactions on electron devices, 2018-03, Vol.65 (3), p.855-859

2018

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Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard

Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack

Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

Bilayered Oxide Heterostructure‐Mediated Capacitance‐Based Neuroplasticity Modulation for Neuromorphic Classification

Impact of the Barrier Layer on the High Thermal and Mechanical Stability of a Flexible Resistive Memory in a Neural Network Application

Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Performance-Aware Corner Model for Design for Manufacturing

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations

Modeling Advanced FET Technology in a Compact Model

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

A Novel Three-Dimensional 6T-SRAM Cell Featuring Vertical Transistors and 24F2 Layout Area

TCAD-Based RF performance prediction and process optimization of 3D monolithically stacked complementary FET

Automated extraction of barrier heights for asymmetric MIM tunneling diodes

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

HfTaO x Rectifying Layer for HfO x ‑Based RRAM for High-Accuracy Neuromorphic Computing Applications

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

Global parameter extraction for a multi-gate MOSFETs compact model

Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering

Computing-in-Memory with Ferroelectric Materials and Beyond

An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

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