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A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS

2017 Symposium on VLSI Circuits, 2017, p.C234-C235

2017

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A 2.5 Gbps CMOS optical receiver analog front-end

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2002, p.359-362

2002

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20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.330-332

2019

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27.5 An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.378-380

2021

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A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

2012 IEEE International Solid-State Circuits Conference, 2012, p.172-174

2012

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A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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850/940-nm VCSEL for optical communication and 3D sensing

Opto-Electronic Advances, 2018-01, Vol.1 (3), p.18000501-18000511

2018

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Analytical Modeling of Current Gain in Multiple-Quantum-Well Heterojunction Bipolar Light-Emitting Transistors

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.1-7

2024

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Bandwidth enhancement techniques for transimpedance amplifier in CMOS technologies

Proceedings of the 27th European Solid-State Circuits Conference, 2001, p.174-177

2001

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Breast carcinoma-amplified sequence 2 regulates adult neurogenesis via [beta]-catenin

Stem cell research & therapy, 2022-04, Vol.13 (1)

2022

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Breast carcinoma-amplified sequence 2 regulates adult neurogenesis via β-catenin

Stem cell research & therapy, 2022-04, Vol.13 (1), p.160-160, Article 160

2022

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The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

Applied physics letters, 2004-10, Vol.85 (16), p.3525-3527

2004

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D-Shaped Silicon-Cored Fibers as Platform to Build In-Line Schottky Photodetectors

IEEE photonics technology letters, 2021-03, Vol.33 (6), p.317-320

2021

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Deep Sub-Micron Strained Si 0.85 Ge 0.15 Channel p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) with Ultra-Thin N 2 O-Annealed SiN Gate Dielectric

Japanese Journal of Applied Physics, 2005-02, Vol.44 (2L), p.L278

2005

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Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS 2 Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5381-5386

2019

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Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO } /Si Substrates Using Area-Selective CVD Technology

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5381-5386

2019

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Derivation and Validation of a Discharge Disposition Predicting Model after Acute Stroke

Journal of stroke and cerebrovascular diseases, 2015-06, Vol.24 (6), p.1179-1186

2015

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Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-[mu]m digital CMOS technology

IEEE transactions on circuits and systems. I, Regular papers, 2006-05, Vol.53 (5), p.977

2006

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Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-05, Vol.53 (5), p.977-983

2006

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Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35- mu m digital CMOS technology

IEEE transactions on circuits and systems. I, Regular papers, 2006, Vol.53 (5)

2006

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Design, Modeling, and Fabrication of High-Speed VCSEL with Data Rate up to 50 Gb/s

Nanoscale research letters, 2019-08, Vol.14 (1), p.276-6, Article 276

2019

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Effect of Quantum-Well Number on the Current Gain of Heterojunction Bipolar Light-Emitting Transistors

2023 Conference on Lasers and Electro-Optics (CLEO), 2023, p.1-2

2023

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Effects of Low-temperature NH[sub 3] Treatment on the Characteristics of HfO[sub 2]∕SiO[sub 2] Gate Stack

Journal of the Electrochemical Society, 2005, Vol.152 (11), p.G799

2005

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Effects of Postdeposition Annealing on the Characteristics of HfO[sub x]N[sub y] Dielectrics on Germanium and Silicon Substrates

Journal of the Electrochemical Society, 2006, Vol.153 (7), p.F160

2006

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Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-[Formula Omitted] Gate Dielectrics

IEEE transactions on electron devices, 2008-04, Vol.55 (4), p.1027-1034

2008

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A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS

A 2.5 Gbps CMOS optical receiver analog front-end

20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET

27.5 An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

850/940-nm VCSEL for optical communication and 3D sensing

Analytical Modeling of Current Gain in Multiple-Quantum-Well Heterojunction Bipolar Light-Emitting Transistors

Bandwidth enhancement techniques for transimpedance amplifier in CMOS technologies

Breast carcinoma-amplified sequence 2 regulates adult neurogenesis via [beta]-catenin

Breast carcinoma-amplified sequence 2 regulates adult neurogenesis via β-catenin

The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

D-Shaped Silicon-Cored Fibers as Platform to Build In-Line Schottky Photodetectors

Deep Sub-Micron Strained Si 0.85 Ge 0.15 Channel p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) with Ultra-Thin N 2 O-Annealed SiN Gate Dielectric

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS 2 Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO } /Si Substrates Using Area-Selective CVD Technology

Derivation and Validation of a Discharge Disposition Predicting Model after Acute Stroke

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-[mu]m digital CMOS technology

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35- mu m digital CMOS technology

Design, Modeling, and Fabrication of High-Speed VCSEL with Data Rate up to 50 Gb/s

Effect of Quantum-Well Number on the Current Gain of Heterojunction Bipolar Light-Emitting Transistors

Effects of Low-temperature NH[sub 3] Treatment on the Characteristics of HfO[sub 2]∕SiO[sub 2] Gate Stack

Effects of Postdeposition Annealing on the Characteristics of HfO[sub x]N[sub y] Dielectrics on Germanium and Silicon Substrates

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-[Formula Omitted] Gate Dielectrics

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