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Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2719-2725

2011

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Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

IEEE transactions on nuclear science, 2011-06, Vol.58 (3), p.1008-1014

2011

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Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4368-4373

2013

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Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4200-4206

2013

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Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2796-2802

2012

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On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2748-2755

2012

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Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.3033-3037

2011

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Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4399-4404

2013

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A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

IEEE transactions on nuclear science, 2006-12, Vol.53 (6), p.3432-3438

2006

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Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4498-4504

2013

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Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2867-2871

2012

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Influence of N-Well Contact Area on the Pulse Width of Single-Event Transients

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2585-2590

2011

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Analysis of Single-Event Transients (SETs) Using Machine Learning (ML) and Ionizing Radiation Effects Spectroscopy (IRES)

IEEE transactions on nuclear science, 2021-08, Vol.68 (8), p.1600-1606

2021

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Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2651-2657

2012

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Supervised Deep Learning and Classification of Single-Event Transients

IEEE transactions on nuclear science, 2023-08, Vol.70 (8), p.1-1

2023

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Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4394-4398

2013

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Effects of Total Ionizing Dose on SRAM Physical Unclonable Functions

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.349-358

2022

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Analysis of Single Event Transients in Arbitrary Waveforms Using Statistical Window Analysis

IEEE transactions on nuclear science, 2023-04, Vol.70 (4), p.478-485

2023

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Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver

IEEE transactions on nuclear science, 2009-12, Vol.56 (6), p.3463-3468

2009

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Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

IEEE transactions on nuclear science, 2020-06, Vol.67 (6), p.1144-1151

2020

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Ionizing Radiation Effects Spectroscopy for Analysis of Total-Ionizing Dose Degradation in RF Circuits

IEEE transactions on nuclear science, 2019-01, Vol.66 (1), p.61-68

2019

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Estimating Single-Event Logic Cross Sections in Advanced Technologies

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2115-2121

2017

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Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.204-211

2017

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A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits

IEEE transactions on nuclear science, 2008-12, Vol.55 (6), p.3130-3135

2008

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Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2561-2567

2007

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Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

Influence of N-Well Contact Area on the Pulse Width of Single-Event Transients

Analysis of Single-Event Transients (SETs) Using Machine Learning (ML) and Ionizing Radiation Effects Spectroscopy (IRES)

Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

Supervised Deep Learning and Classification of Single-Event Transients

Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes

Effects of Total Ionizing Dose on SRAM Physical Unclonable Functions

Analysis of Single Event Transients in Arbitrary Waveforms Using Statistical Window Analysis

Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver

Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

Ionizing Radiation Effects Spectroscopy for Analysis of Total-Ionizing Dose Degradation in RF Circuits

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology

A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits

Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

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