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Mesoporous SSZ-13 zeolite prepared by a dual-template method with improved performance in the methanol-to-olefins reaction

Journal of catalysis, 2013-02, Vol.298, p.27-40

2013

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Wrapper design for embedded core test

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000, p.911-920

2000

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A structured and scalable mechanism for test access to embedded reusable cores

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 1998, p.284-293

1998

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IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

Electronics letters, 2007, Vol.43 (5), p.273-274

2007

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An effective diagnosis method to support yield improvement

Proceedings - International Test Conference, 2002, p.260-269

2002

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CTL the language for describing core-based test

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.131-139

2001

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Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000, p.95-104

2000

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Memory testing improvements through different stress conditions

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005, 2005, p.299-302

2005

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On IEEE P1500's Standard for Embedded Core Test

Journal of electronic testing, 2002-08, Vol.18 (4-5), p.365

2002

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Improving diagnostic resolution of delay faults using path delay fault model

Proceedings. 21st VLSI Test Symposium, 2003, 2003, p.345-350

2003

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I^sub DDQ^-based diagnosis at very low voltage (VLV) for bridging defects

Electronics letters, 2007-03, Vol.43 (5), p.1

2007

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I sub( DDQ)-based diagnosis at very low voltage (VLV) for bridging defects

Electronics letters, 2007-03, Vol.43 (5), p.1-1

2007

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TAPs all over my chips

Proceedings. International Test Conference, 2002, p.1189

Lousberg, M.

2002

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Sensemaking in the Park – Keeping the Story Alive

Procedia, social and behavioral sciences, 2015-07, Vol.194, p.96-104

2015

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Biomimetic synthesis of calcium carbonate bilayers interfaced by a diblock copolymer template

Zeitschrift für Kristallographie. Crystalline materials, 2012-11, Vol.227 (11), p.739-743

2012

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Defect-based delay testing of resistive vias-contacts a critical evaluation

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.467-476

1999

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Diagnosis of Full Open Defects in Interconnecting Lines

25th IEEE VLSI Test Symposium (VTS'07), 2007, p.158-166

2007

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IEEE Std 1500 Compliant Infrastructure forModular SOC Testing

14th Asian Test Symposium (ATS'05), 2005, p.450-450

2005

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Managing economic feasibility and social relationships: interventions to prevent dysfunctional conflict in public–private partnerships

Engineering project organization journal, 2016-10, Vol.6 (2-4), p.166-175

2016

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On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up

Journal of electronic testing, 2003-08, Vol.19 (4), p.369-376

2003

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Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

25th IEEE VLSI Test Symposium (VTS'07), 2007, p.145-150

2007

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Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Design, Automation and Test in Europe, 2005, p.438-443

2005

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Case study: suspending patient services in a community hospital during a union strike

Case studies in health administration, 1987, Vol.6, p.102

Lousberg, M C

1987

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A new algorithm for dynamic faults detection in RAMs

23rd IEEE VLSI Test Symposium (VTS'05), 2005, p.177-182

2005

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Static component interconnect test technology (SCITT) a new technology for assembly testing

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.439-448

1999

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Mesoporous SSZ-13 zeolite prepared by a dual-template method with improved performance in the methanol-to-olefins reaction

Wrapper design for embedded core test

A structured and scalable mechanism for test access to embedded reusable cores

IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

An effective diagnosis method to support yield improvement

CTL the language for describing core-based test

Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?

Memory testing improvements through different stress conditions

On IEEE P1500's Standard for Embedded Core Test

Improving diagnostic resolution of delay faults using path delay fault model

I^sub DDQ^-based diagnosis at very low voltage (VLV) for bridging defects

I sub( DDQ)-based diagnosis at very low voltage (VLV) for bridging defects

TAPs all over my chips

Sensemaking in the Park – Keeping the Story Alive

Biomimetic synthesis of calcium carbonate bilayers interfaced by a diblock copolymer template

Defect-based delay testing of resistive vias-contacts a critical evaluation

Diagnosis of Full Open Defects in Interconnecting Lines

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing

Managing economic feasibility and social relationships: interventions to prevent dysfunctional conflict in public–private partnerships

On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Case study: suspending patient services in a community hospital during a union strike

A new algorithm for dynamic faults detection in RAMs

Static component interconnect test technology (SCITT) a new technology for assembly testing

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