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Parallel unidirectional division algorithms and implementations parallel unidirectional division algorithms and implementations

Journal of the Chinese Institute of Engineers, 2001-06, Vol.24 (4), p.487-496

2001

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An implementation of the conditional-sum scheme embedded in a signed digital adder

Journal of the Chinese Institute of Engineers, 1996-07, Vol.19 (5), p.633-643

Lo, Hao-Yung

1996

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A UNIDIRECTIONAL CORDIC ALGORITHM FOR ANGL COMPUTATION AND ROTATION

Journal of the Chinese Institute of Engineers, 1997-11, Vol.20 (6), p.693-700

Lo, Hao-Yung

1997

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A new design of a balanced and self-purging cascaded n-module redundancy (NMR)

Journal of the Chinese Institute of Engineers, 1995-01, Vol.18 (1), p.11-23

1995

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A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration

IEEE transactions on computers, 1987-11, Vol.C-36 (11), p.1363-1367

1987

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Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

Journal of electronic testing, 2003-06, Vol.19 (3), p.245-269

2003

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Parallel Algorithms for Residue Scaling and Error Correction in Residue Arithmetic

Wireless engineering and technology, 2013-09, Vol.4 (4), p.198-213

2013

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High-speed signed digital multipiers for VLSI

Microprocessing and microprogramming, 1990, Vol.29 (4), p.205-215

Lo, Hao-Yung

1990

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Highly efficient flexible-purging redundancy scheme

International journal of electronics, 1989-07, Vol.67 (1), p.1-6

1989

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Novel high reliability bus level voted microcomputer system

International journal of electronics, 1990-04, Vol.68 (4), p.507-517

1990

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Double-speed quasi-serial multiplier

International journal of electronics, 1989-10, Vol.67 (4), p.523-532

1989

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Microstep of digital control for step motor and its test using a laser interferometer measurement system

International journal of electronics, 1987-05, Vol.62 (5), p.761-780

1987

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A combinational word-parallel and bit-parallel associative processor

International journal of electronics, 1987-04, Vol.62 (4), p.589-598

1987

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An improved non-restoring array divider with carry-save and carry-look-ahead techniques

International journal of electronics, 1987-03, Vol.62 (3), p.441-448

1987

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Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array

IEEE transactions on computers, 1985-08, Vol.C-34 (8), p.681-691

1985

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Priority switch design for hybrid redundancy system

International journal of electronics, 1989, Vol.66 (6), p.879-885

1989

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A high-speed of self-timing carry-completion for direct two's complement multipliers

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242), 1998, p.643-646

1998

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A distributive D-algorithm for generating the test pattern for faulty combinational circuit

International journal of electronics, 1989-01, Vol.66 (1), p.35-42

1989

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Balanced high-speed residue number VLSI multiplier with error detection

IEE proceedings. G, Circuits, devices, and systems, 1991-06, Vol.138 (3), p.421

1991

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A compromise between speed and complexity in a BCD adder

International journal of electronics, 1979-01, Vol.46 (1), p.75-79

LO, HAO-YUNG

1979

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Design of microcomputer-based data acquisition system for the time-of-flight ion scattering spectrometer

Nuclear instruments and methods in physics research, 1981-01, Vol.186 (3), p.637-640

1981

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Binary logarithms for computing integral and non-integral roots and powers

International journal of electronics, 1976-04, Vol.40 (4), p.357-364

LO, HAO-YUNG

1976

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A simple design for a digital programmable frequency multiplier

International journal of electronics, 1979-05, Vol.46 (5), p.535-542

1979

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High-Speed Signed Digital Multipliers for VLSI

Journal of systems architecture, 1990-12, Vol.29 (4), p.205

Lo, Hao-Yung

1990

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New D‐A‐A’‐Configured Small Molecule Donors Employing Conjugation to Red‐shift the Absorption for Photovoltaics

Chemistry, an Asian journal, 2020-08, Vol.15 (16), p.2520-2531

2020

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Parallel unidirectional division algorithms and implementations parallel unidirectional division algorithms and implementations

An implementation of the conditional-sum scheme embedded in a signed digital adder

A UNIDIRECTIONAL CORDIC ALGORITHM FOR ANGL COMPUTATION AND ROTATION

A new design of a balanced and self-purging cascaded n-module redundancy (NMR)

A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration

Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

Parallel Algorithms for Residue Scaling and Error Correction in Residue Arithmetic

High-speed signed digital multipiers for VLSI

Highly efficient flexible-purging redundancy scheme

Novel high reliability bus level voted microcomputer system

Double-speed quasi-serial multiplier

Microstep of digital control for step motor and its test using a laser interferometer measurement system

A combinational word-parallel and bit-parallel associative processor

An improved non-restoring array divider with carry-save and carry-look-ahead techniques

Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array

Priority switch design for hybrid redundancy system

A high-speed of self-timing carry-completion for direct two's complement multipliers

A distributive D-algorithm for generating the test pattern for faulty combinational circuit

Balanced high-speed residue number VLSI multiplier with error detection

A compromise between speed and complexity in a BCD adder

Design of microcomputer-based data acquisition system for the time-of-flight ion scattering spectrometer

Binary logarithms for computing integral and non-integral roots and powers

A simple design for a digital programmable frequency multiplier

High-Speed Signed Digital Multipliers for VLSI

New D‐A‐A’‐Configured Small Molecule Donors Employing Conjugation to Red‐shift the Absorption for Photovoltaics

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