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0.01％次氯酸在白内障超声乳化术前应用的安全性和有效性

国际眼科杂志, 2024-02, Vol.24 (2), p.264-269

2024

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A 0.02mm2Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-4

2023

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A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.704-713

2024

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A 0.079-pJ/b/dB 32-Gb/s 2 \times Half-Baud-Rate CDR Circuit With Frequency Detector

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, p.1-10

2023

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0.15- mu m T-gate In sub(0.52)Al sub(0.48)As/In sub(0.53)Ga sub(0.47)As InP-based HEMT with [functionof] sub(max) of 390 GHz

Chinese physics B, 2013-12, Vol.22 (12), p.128503-1-128503-5

2013

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0.15-μm T-gate In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As InP-based HEMT with f max of 390 GHz

Chinese physics B, 2013-12, Vol.22 (12), p.128503

2013

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A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, 2006, p.4 pp.-264

2006

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A 0.18-μm 3.3 V 16 k Bits 1R1T Phase Change Random Access Memory (PCRAM) Chip

Chinese physics letters, 2008-10, Vol.25 (10), p.3815-3817

2008

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A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014, p.195-198

2014

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A 0.3-V all digital crystal-less clock generator for energy harvester applications

2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012, p.117-120

2012

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0.3 VT/1.1 kV AlGaN/GaN lateral power diode with MIS-gated hybrid anode on silicon substrate

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016, p.1041-1043

2016

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0—3及4—6周龄肉仔鸡日粮能量及蛋白质沉积效率参数研究

Chung-kuo nung yeh kʿo hsüeh, 2010, Vol.43 (17), p.3624-3632

李勇蔡辉益刘国华杨志刚常文环张妹

2010

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A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.56-67

2016

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A 0.5 to 4.0GHz Low-Cost Broadband GaAs HBT Low Noise Amplifier

2019 IEEE MTT-S International Wireless Symposium (IWS), 2019, p.1-3

2019

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A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4370-4381

2020

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A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction

IEEE journal of solid-state circuits, 2021-05, Vol.56 (5), p.1588-1596

2021

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A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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Al 0.5 Zn 0.5 O:In-Based Photodetectors: Metal–Semiconductor–Metal and Heterojunction for Deep-UV Sensing

IEEE sensors journal, 2023-10, Vol.23 (19), p.22406-22413

2023

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Na 0.56 Ti 1.72 Fe 0.28 O 4 : a novel anode material for Na-ion batteries

RSC advances, 2015, Vol.5 (108), p.88556-88559

2015

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0.5V 160-MHz 260uW all digital phase-locked loop

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2009, p.186-193

2009

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A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, p.33-34

2019

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A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

IEICE Electronics Express, 2016, Vol.13 (2), p.20150950-20150950

2016

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A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.888-892

2012

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A 0.67μW/MHz, 5ps Jitter, 4 Locking Cycles, 65nm ADDLL

2007 IEEE Asian Solid-State Circuits Conference, 2007, p.300-303

2007

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0.01％次氯酸在白内障超声乳化术前应用的安全性和有效性

A 0.02mm2Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

A 0.079-pJ/b/dB 32-Gb/s 2 \times Half-Baud-Rate CDR Circuit With Frequency Detector

0.15- mu m T-gate In sub(0.52)Al sub(0.48)As/In sub(0.53)Ga sub(0.47)As InP-based HEMT with [functionof] sub(max) of 390 GHz

0.15-μm T-gate In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As InP-based HEMT with f max of 390 GHz

A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems

A 0.18-μm 3.3 V 16 k Bits 1R1T Phase Change Random Access Memory (PCRAM) Chip

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

A 0.3-V all digital crystal-less clock generator for energy harvester applications

0.3 VT/1.1 kV AlGaN/GaN lateral power diode with MIS-gated hybrid anode on silicon substrate

0—3及4—6周龄肉仔鸡日粮能量及蛋白质沉积效率参数研究

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

A 0.5 to 4.0GHz Low-Cost Broadband GaAs HBT Low Noise Amplifier

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction

A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique

Al 0.5 Zn 0.5 O:In-Based Photodetectors: Metal–Semiconductor–Metal and Heterojunction for Deep-UV Sensing

Na 0.56 Ti 1.72 Fe 0.28 O 4 : a novel anode material for Na-ion batteries

0.5V 160-MHz 260uW all digital phase-locked loop

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

A 0.67μW/MHz, 5ps Jitter, 4 Locking Cycles, 65nm ADDLL

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