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Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements

IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2271-2284

2017

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An Enhanced Vacuum-Assisted Resin Transfer Molding Process and Its Pressure Effect on Resin Infusion Behavior and Composite Material Performance

Polymers, 2024-05, Vol.16 (10), p.1386

2024

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System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

IEEE transactions on very large scale integration (VLSI) systems, 2016-08, Vol.24 (8), p.2712-2725

2016

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Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

IEEE transactions on emerging topics in computing, 2018-04, Vol.6 (2), p.219-232

2018

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System-level modeling of microprocessor reliability degradation due to BTI and HCI

2014 IEEE International Reliability Physics Symposium, 2014, p.CA.8.1-CA.8.9

2014

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CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3078-3091

2022

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Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

2014 IEEE 32nd VLSI Test Symposium (VTS), 2014, p.1-6

2014

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A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2470-2482

2018

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A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory

IEEE transactions on very large scale integration (VLSI) systems, 2021-05, Vol.29 (5), p.857-870

2021

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SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.620-633

2020

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Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations

Microelectronics and reliability, 2017-09, Vol.76-77, p.87-91

2017

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Impact of front-end wearout mechanisms on FinFET SRAM soft error rate

Microelectronics and reliability, 2019-09, Vol.100-101, p.113487, Article 113487

2019

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A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Microelectronics and reliability, 2019-09, Vol.100-101, p.113486, Article 113486

2019

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The multiparty coherent channel and its implementation with linear optics

Optics express, 2013-08, Vol.21 (17), p.19790-19798

2013

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System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Microelectronics and reliability, 2015-08, Vol.55 (9-10), p.1334-1340

2015

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Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Microelectronics and reliability, 2017-09, Vol.76-77, p.81-86

2017

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Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology

2018 IEEE 36th VLSI Test Symposium (VTS), 2018, p.1-6

2018

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Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Microelectronics and reliability, 2015-08, Vol.55 (9-10), p.1290-1296

2015

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On-line monitoring of system health using on-chip SRAMs as a wearout sensor

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, p.253-258

2017

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Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

2017 IEEE International Integrated Reliability Workshop (IIRW), 2017, p.1-4

2017

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A comparison study of time-dependent dielectric breakdown for analog and digital circuit's optimal accelerated test regions

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017, p.1-6

2017

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SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection

2016 IEEE 34th International Conference on Computer Design (ICCD), 2016, p.225-232

2016

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Modeling for SRAM reliability degradation due to gate oxide breakdown with a compact current model

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017, p.1-5

2017

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Inverse Design of FinFET SRAM Cells

2020 IEEE International Reliability Physics Symposium (IRPS), 2020, p.1-6

2020

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New Electromigration Model and Its Potential Application on Degradation Simulation for FinFET SRAM

2018 International Integrated Reliability Workshop (IIRW), 2018, p.1-5

2018

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Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements

An Enhanced Vacuum-Assisted Resin Transfer Molding Process and Its Pressure Effect on Resin Infusion Behavior and Composite Material Performance

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

System-level modeling of microprocessor reliability degradation due to BTI and HCI

CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory

SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations

Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations

Impact of front-end wearout mechanisms on FinFET SRAM soft error rate

A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

The multiparty coherent channel and its implementation with linear optics

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

On-line monitoring of system health using on-chip SRAMs as a wearout sensor

Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

A comparison study of time-dependent dielectric breakdown for analog and digital circuit's optimal accelerated test regions

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection

Modeling for SRAM reliability degradation due to gate oxide breakdown with a compact current model

Inverse Design of FinFET SRAM Cells

New Electromigration Model and Its Potential Application on Degradation Simulation for FinFET SRAM

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