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A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

IEEE journal of solid-state circuits, 2016-04, Vol.51 (4), p.821-831

2016

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A Voltage Multiplier With Adaptive Threshold Voltage Compensation

IEEE journal of solid-state circuits, 2017-08, Vol.52 (8), p.2208-2214

2017

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Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique

IEEE transactions on circuits and systems. I, Regular papers, 2012-02, Vol.59 (2), p.305-314

2012

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A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers

IEEE journal of solid-state circuits, 2007-02, Vol.42 (2), p.329-339

2007

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A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2474-2478

2020

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A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

IEEE journal of solid-state circuits, 2013-02, Vol.48 (2), p.417-428

2013

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A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2013-12, Vol.60 (12), p.837-841

2013

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A Loop Gain Optimization Technique for Integer- N TDC-Based Phase-Locked Loops

IEEE transactions on circuits and systems. I, Regular papers, 2015-07, Vol.62 (7), p.1873-1882

2015

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A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

IEEE transactions on circuits and systems. I, Regular papers, 2018-06, Vol.65 (6), p.1830-1839

2018

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A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop

IEEE transactions on circuits and systems. I, Regular papers, 2017-04, Vol.64 (4), p.811-822

2017

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40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

IEEE journal of solid-state circuits, 2008-03, Vol.43 (3), p.642-655

2008

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A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

IEEE journal of solid-state circuits, 2007-02, Vol.42 (2), p.361-373

2007

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A Current-Reused Injection-Locked Frequency Multiplication/Division Circuit in 40-nm CMOS

IEEE transactions on microwave theory and techniques, 2013-04, Vol.61 (4), p.1523-1532

2013

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A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection

IEEE journal of solid-state circuits, 2013-02, Vol.48 (2), p.391-404

2013

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A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3111-3119

2009

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Analysis and Design of D-Band Injection-Locked Frequency Dividers

IEEE journal of solid-state circuits, 2011-06, Vol.46 (6), p.1250-1264

2011

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A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

IEEE transactions on circuits and systems. II, Express briefs, 2011-06, Vol.58 (6), p.321-325

2011

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A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 mu m CMOS Technology

IEEE journal of solid-state circuits, 2007-11, Vol.42 (11)

2007

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A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2815-2826

2013

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A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time

IEEE transactions on circuits and systems. II, Express briefs, 2016-02, Vol.63 (2), p.126-130

2016

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A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

IEEE journal of solid-state circuits, 2023-03, Vol.58 (3), p.1-11

2023

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A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.704-713

2024

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A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.787-791

2024

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A Digital PLL Using Oversampling Delta-Sigma TDC

IEEE transactions on circuits and systems. II, Express briefs, 2016-07, Vol.63 (7), p.633-637

2016

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A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

IEEE transactions on circuits and systems. II, Express briefs, 2024-09, Vol.71 (9), p.4156-4160

2024

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A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

A Voltage Multiplier With Adaptive Threshold Voltage Compensation

Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique

A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers

A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation

A Loop Gain Optimization Technique for Integer- N TDC-Based Phase-Locked Loops

A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

A Current-Reused Injection-Locked Frequency Multiplication/Division Circuit in 40-nm CMOS

A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection

A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

Analysis and Design of D-Band Injection-Locked Frequency Dividers

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 mu m CMOS Technology

A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection

A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection

A Digital PLL Using Oversampling Delta-Sigma TDC

A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

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