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Performance of piles with different configurations subjected to slope deformation induced by seismic liquefaction

Engineering geology, 2019-12, Vol.263, p.105355, Article 105355

2019

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A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

IEEE journal of solid-state circuits, 2020-09, Vol.55 (9), p.2371-2386

2020

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64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2871-2891

2017

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A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components

IEICE transactions on electronics, 2022-07, Vol.E105.C (7), p.334-342, Article 2021CDP0003

2022

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21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.344-346

2019

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Shaking table tests on mitigation of liquefaction vulnerability for existing embedded lifelines

Soils and foundations, 2016-06, Vol.56 (3), p.348-364

2016

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A Low-Jitter Injection-Locked Clock Multiplier Using 97-µW Transformer-Based VCO with 18-kHz Flicker Noise Corner

IEICE transactions on electronics, 2021-07, Vol.E104.C (7), p.289-299, Article 2020CDP0005

2021

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Optimization of Location of Robotic Total Station in Tunnel Deformation Monitoring

Proceedings of China-Europe Conference on Geotechnical Engineering, p.707-711

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A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications

IEICE transactions on electronics, 2020-10, Vol.E103.C (10), p.505-513

2020

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A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

IEICE transactions on electronics, 2019-04, Vol.E102.C (4), p.276-286

2019

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A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio

2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018, p.56-59

2018

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A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.101-104

2019

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An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.197-200

2016

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A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS

IEICE transactions on electronics, 2018-01, Vol.E101.C (2), p.126-134

2018

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An Internet Based Intelligent System for Early Concrete Curing in Underground Structures

Proceedings of China-Europe Conference on Geotechnical Engineering, p.743-746

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A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

IEEE journal of solid-state circuits, 2020-05, Vol.55 (5), p.1-1

2020

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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, p.1-4

2018

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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1228-1242

2019

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Shaking table tests on liquefaction mitigation of embedded lifelines by backfilling with recycled materials

Soils and foundations, 2016-06, Vol.56 (3), p.365-378

2016

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A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving - 52.79-dBc Fractional Spur With 50-MHz Reference

IEEE journal of solid-state circuits, 2024-08, p.1-13

2024

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A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1375-1390

2019

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A low-power digital baseband circuit for GMSK demodulation in sub-GHz application

IEICE Electronics Express, 2022-06, Vol.19 (12), p.20220201-20220201, Article 19.20220201

2022

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A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1310-1326

2021

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A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

IEEE journal of solid-state circuits, 2021-12, Vol.56 (12), p.3741-3755

2021

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A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.993-1005

2024

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Performance of piles with different configurations subjected to slope deformation induced by seismic liquefaction

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components

21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

Shaking table tests on mitigation of liquefaction vulnerability for existing embedded lifelines

A Low-Jitter Injection-Locked Clock Multiplier Using 97-µW Transformer-Based VCO with 18-kHz Flicker Noise Corner

Optimization of Location of Robotic Total Station in Tunnel Deformation Monitoring

A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio

A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO

An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS

An Internet Based Intelligent System for Early Concrete Curing in Underground Structures

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

Shaking table tests on liquefaction mitigation of embedded lifelines by backfilling with recycled materials

A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving - 52.79-dBc Fractional Spur With 50-MHz Reference

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

A low-power digital baseband circuit for GMSK demodulation in sub-GHz application

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter

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