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Thermal effect of 0.1 μm partially depleted SOI CMOSFET

Microelectronic engineering, 2001-11, Vol.59 (1), p.475-482

2001

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Reactively sputtered titanium nitride films for submicron contact barrier metallization

Applied physics letters, 1993-01, Vol.62 (4), p.357-359

1993

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Identification of Si / SiO2 Interface Properties in Thin Film Transistors with Charge Pumping Technique

Journal of the Electrochemical Society, 1995-08, Vol.142 (8), p.2717-2721

1995

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Mechanism of Threshold Voltage Shift (Δ V th ) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

Japanese Journal of Applied Physics, 2002, Vol.41 (Part 1, No. 4B), p.2423-2425

2002

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Transmission electron microscopy characterization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process

Applied physics letters, 1992-05, Vol.60 (18), p.2228-2230

1992

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Hole current in dual dielectric under positive gate voltage

IEEE electron device letters, 1983-08, Vol.4 (8), p.261-263

1983

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Observation of two types of trapping centers in thin film transistors using charge pumping technique

IEEE electron device letters, 1995-10, Vol.16 (10), p.460-462

1995

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Solid electrochemical modification of semiconductors

Solid state communications, 1982-01, Vol.43 (8), p.633-636

1982

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Polycrystalline In2O3 and In2O3/Y2O3 photoanodes

Journal of applied electrochemistry, 1983-05, Vol.13 (3), p.377-382

1983

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Thin Dielectric Quality/Yield Study Using a Constant Voltage Ramp Method

Journal of the Electrochemical Society, 1989-01, Vol.136 (1), p.283-287

1989

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A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

IEEE journal of solid-state circuits, 1989-04, Vol.24 (2), p.380-387

1989

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Characterization of TiN Diffusion Barrier for Submicron Technology

MRS proceedings, 1992, Vol.260, Article 833

1992

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Advanced Planarized Aluminum Metallization Process

MRS proceedings, 1992, Vol.260, Article 617

1992

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Thermal Stability of Sputter Deposited Tantallum Silicide Films

MRS proceedings, 1991, Vol.225, Article 237

1991

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A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12∼16A) gate oxide

2002

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Characterization Study of Al-Plug Technology

MRS proceedings, 1991, Vol.225, Article 79

1991

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Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping

Proceedings of International Electron Devices Meeting, 1995, p.529-532

1995

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Transmission electron microscopy characterization of defects resulting from th epolycrystalline silicon buffered local oxidation of silicon isolation process

Applied physics letters, 1992, Vol.60 (18), p.2228-2230

1992

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A 0.8-mu m CMOS technology for high-performance ASIC memory andchannelless gate array

IEEE journal of solid-state circuits, 1989-04, Vol.24 (2), p.380-387

1989

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Evidence of hole flow in silicon nitride for positive gate voltage

IEEE transactions on electron devices, 1984-12, Vol.31 (12), p.1736-1741

1984

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Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, 1991, p.109-112

1991

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Polycrystalline In sub(2)O sub(3) and In sub(2)O sub(3)/Y sub(2)O sub(3) photoanodes

Journal of applied electrochemistry, 1983-01, Vol.13 (3), p.377-382

1983

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A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, 1991, p.362-365

1991

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A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, p.74-75

2002

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Thermal effect of 0.1 μm partially depleted SOI CMOSFET

Reactively sputtered titanium nitride films for submicron contact barrier metallization

Identification of Si / SiO2 Interface Properties in Thin Film Transistors with Charge Pumping Technique

Mechanism of Threshold Voltage Shift (Δ V th ) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

Transmission electron microscopy characterization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process

Hole current in dual dielectric under positive gate voltage

Observation of two types of trapping centers in thin film transistors using charge pumping technique

Solid electrochemical modification of semiconductors

Polycrystalline In2O3 and In2O3/Y2O3 photoanodes

Thin Dielectric Quality/Yield Study Using a Constant Voltage Ramp Method

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

Characterization of TiN Diffusion Barrier for Submicron Technology

Advanced Planarized Aluminum Metallization Process

Thermal Stability of Sputter Deposited Tantallum Silicide Films

A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12∼16A) gate oxide

Characterization Study of Al-Plug Technology

Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping

Transmission electron microscopy characterization of defects resulting from th epolycrystalline silicon buffered local oxidation of silicon isolation process

A 0.8-mu m CMOS technology for high-performance ASIC memory andchannelless gate array

Evidence of hole flow in silicon nitride for positive gate voltage

Extending the reliability scaling limit of gate dielectrics through remote plasma nitridation of N2O-Grown oxides and NO RTA treatment

Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology

Polycrystalline In sub(2)O sub(3) and In sub(2)O sub(3)/Y sub(2)O sub(3) photoanodes

A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process

A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide

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