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0.005% Preservative-Free Latanoprost Induces Dry Eye-Like Ocular Surface Damage via Promotion of Inflammation in Mice

Investigative ophthalmology & visual science, 2018-07, Vol.59 (8), p.3375-3384

2018

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A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager

2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012, p.165-168

2012

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0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, 2005, p.911-914

2005

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In 0.11 Ga 0.89 N‐based p‐i‐n photodetector

Physica status solidi. C, 2009-06, Vol.6 (S2)

2009

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A 0.13 [Formula Omitted]m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1454-1463

2009

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A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

IEEE journal of solid-state circuits, 2013-05, Vol.48 (5), p.1315-1322

2013

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A 0.13 \mu m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1454-1463

2009

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A 0.13 µm 8 Mb Logic-Based Cu Si O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

IEEE journal of solid-state circuits, 2013-05, Vol.48 (5), p.1315-1322

2013

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A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.42-43

2012

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0.18 Micron BiCMOS Process with Novel Structure SiGeC HBT

ECS transactions, 2011, Vol.34 (1), p.173-181

2011

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A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.534-536 Vol.1

2003

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A 0.18 μm CMOS 3-5GHz switched gain low noise amplifier for UWB system

2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2009, p.162-165

2009

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A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

Journal of semiconductors, 2012-02, Vol.33 (2), p.25004-1-5

2012

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A 0.18 μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

Journal of semiconductors, 2010-12, Vol.31 (12), p.125006

2010

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A 0.18 μm mixer merged with LNA exploiting noise cancellation

2011 IEEE International Symposium on Radio-Frequency Integration Technology, 2011, p.25-28

2011

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A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

半导体学报, 2012, Vol.33 (2), p.77-81

孙景业黄鲁袁海泉林福江

2012

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A 0.18μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

Journal of semiconductors, 2010 (12), p.123-128

Yuan Haiquan Lin Fujiang Fu Zhongqian Huang Lu

2010

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0.2–4.35 GHz highly linear CMOS balun-LNA with substrate noise optimization

Analog integrated circuits and signal processing, 2015-06, Vol.83 (3), p.285-293

2015

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A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

International journal of electronics and communications, 2018-02, Vol.84, p.192-198

2018

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A 0.33-V, 500-kHz, 3.94-[Formula Omitted] 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.863-867

2012

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A 0.33-V, 500-kHz, 3.94- \mu\hbox 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.863-867

2012

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A 0.33 V 683 \mu K-Band Transformer-Based Receiver Front-End in 65 nm CMOS Technology

IEEE microwave and wireless components letters, 2015-03, Vol.25 (3), p.184-186

2015

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A 0.33 V 683 mu rmW K-Band Transformer-Based Receiver Front-End in 65 nm CMOS Technology

IEEE microwave and wireless components letters, 2015-03, Vol.25 (3), p.184-186

2015

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0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.129-132

2014

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0.005% Preservative-Free Latanoprost Induces Dry Eye-Like Ocular Surface Damage via Promotion of Inflammation in Mice

A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager

0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications

In 0.11 Ga 0.89 N‐based p‐i‐n photodetector

A 0.13 [Formula Omitted]m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

A 0.13 \mu m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

A 0.13 µm 8 Mb Logic-Based Cu Si O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction

0.18 Micron BiCMOS Process with Novel Structure SiGeC HBT

A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction

A 0.18 μm CMOS 3-5GHz switched gain low noise amplifier for UWB system

A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

A 0.18 μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

A 0.18 μm mixer merged with LNA exploiting noise cancellation

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

A 0.18μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

0.2–4.35 GHz highly linear CMOS balun-LNA with substrate noise optimization

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

A 0.33-V, 500-kHz, 3.94-[Formula Omitted] 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

A 0.33-V, 500-kHz, 3.94- \mu\hbox 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

A 0.33 V 683 \mu K-Band Transformer-Based Receiver Front-End in 65 nm CMOS Technology

A 0.33 V 683 mu rmW K-Band Transformer-Based Receiver Front-End in 65 nm CMOS Technology

0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS

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