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Trap-Assisted DRAM Row Hammer Effect

IEEE electron device letters, 2019-03, Vol.40 (3), p.391-394

2019

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IEEE_Xplore

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

IEEE electron device letters, 2017-12, Vol.38 (12), p.1657-1660

2017

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IEEE_Xplore

Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

IEEE transactions on electron devices, 2024-03, Vol.71 (3), p.1893-1899

2024

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IEEE_Xplore

Investigation of Random Telegraph Noise Under Different Programmed Cell Vt Levels in Charge Trap Based 3D NAND Flash

IEEE electron device letters, 2022-06, Vol.43 (6), p.878-881

2022

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IEEE_Xplore

Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.7B.5-1-7B.5-6

2024

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IEEE_Xplore

Intentional Distortion of Transistor Shape to Improve Circuit Performance

IEEE electron device letters, 2010-01, Vol.31 (1), p.62-64

2010

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IEEE_Xplore

High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach

2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2020, p.35-38

2020

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IEEE_Xplore

Understanding the impact of polysilicon percolative conduction on 3D NAND variability

2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2023, p.97-100

2023

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Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.188-191

2021

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IEEE_Xplore

Challenges in Design and Modeling of Cold CMOS HPC Technology

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.107-110

2021

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IEEE_Xplore

Modeling and Optimization of Advanced 3D NAND Memory

2020 Device Research Conference (DRC), 2020, p.1-2

2020

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IEEE_Xplore

Power-performance-area engineering of 5nm nanowire library cells

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.433-436

2015

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IEEE_Xplore

Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies

Journal of microelectronic manufacturing, 2020-12, Vol.3 (4), p.1-8

2020

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Synthesis of superhard carbon nitride composite coatings

Applied physics letters, 1995-07, Vol.67 (2), p.203-205

1995

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Feature Extraction and Classification of Human Brain CT Image

Lin, Xi Wei

2008

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Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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IEEE_Xplore

Logic Block Level Design-Technology Co-Optimization is the New Moore's Law (Invited)

2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020, p.1-4

2020

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Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects

MRS proceedings, 2008, Vol.1079 (1), Article 1079-N09-09

2008

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Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

MRS proceedings, 2007, Vol.990, Article 0990-B10-02

2007

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A Multiscale Statistical Evaluation of DRAM Variable Retention Time

2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021, p.1-3

2021

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Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.5.5.1-5.5.4

2015

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IEEE_Xplore

Layout Proximity Effects and Modeling Alternatives for IC Designs

IEEE design & test of computers, 2010-03, Vol.27 (2), p.18-25

2010

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IEEE_Xplore

Investigation of Random Telegraph Noise Under Different Programmed Cell V t Levels in Charge Trap Based 3D NAND Flash

IEEE electron device letters, 2022-06, Vol.43 (6), p.878-881

2022

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Transmission spectrum of coaxial localized-defected Bragg structures with uniform and inhomogeneous ripples

Asia-Pacific Microwave Conference 2011, 2011, p.813-816

2011

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IEEE_Xplore

Effect of defect location and corrugation phase on transmission in a defected coaxial Bragg structure with two corrugated surfaces

2012 Asia Pacific Microwave Conference Proceedings, 2012, p.556-558

2012

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IEEE_Xplore

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Trap-Assisted DRAM Row Hammer Effect

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

Investigation of Random Telegraph Noise Under Different Programmed Cell Vt Levels in Charge Trap Based 3D NAND Flash

Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology

Intentional Distortion of Transistor Shape to Improve Circuit Performance

High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach

Understanding the impact of polysilicon percolative conduction on 3D NAND variability

Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter

Challenges in Design and Modeling of Cold CMOS HPC Technology

Modeling and Optimization of Advanced 3D NAND Memory

Power-performance-area engineering of 5nm nanowire library cells

Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies

Synthesis of superhard carbon nitride composite coatings

Feature Extraction and Classification of Human Brain CT Image

Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

Logic Block Level Design-Technology Co-Optimization is the New Moore's Law (Invited)

Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects

Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

A Multiscale Statistical Evaluation of DRAM Variable Retention Time

Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

Layout Proximity Effects and Modeling Alternatives for IC Designs

Investigation of Random Telegraph Noise Under Different Programmed Cell V t Levels in Charge Trap Based 3D NAND Flash

Transmission spectrum of coaxial localized-defected Bragg structures with uniform and inhomogeneous ripples

Effect of defect location and corrugation phase on transmission in a defected coaxial Bragg structure with two corrugated surfaces

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