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Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding

IEEE transactions on circuits and systems. I, Regular papers, 2008-08, Vol.55 (7), p.1911-1920

Lin, Rung-Bin

2008

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2^ Pattern Run-Length for Test Data Compression

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-04, Vol.31 (4), p.644-648

2012

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Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

IEEE transactions on very large scale integration (VLSI) systems, 2012-12, Vol.20 (12), p.2184-2197

2012

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An Internal Pattern Run‐Length Methodology for Slice Encoding

ETRI Journal, 2011, 33(3), , pp.374-381

2011

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A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction

ACM transactions on design automation of electronic systems, 2018-07, Vol.23 (4), p.1-26

2018

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Improving Pin Accessibility of Standard Cells under Power/Ground Stripes

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023, p.1-5

2023

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Routing Intent Aware Pin Access Point Selection for Standard Cell Designs

2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, p.1-8

2024

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Theoretical analysis of bus-invert coding

IEEE transactions on very large scale integration (VLSI) systems, 2002-12, Vol.10 (6), p.929-934

2002

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Reduction of power dissipation during scan testing by test vector ordering

Journal of the Chinese Institute of Engineers, 2010-03, Vol.33 (2), p.263-270

2010

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Reticle Design for Minimizing Multiproject Wafer Production Cost

IEEE transactions on automation science and engineering, 2007-10, Vol.4 (4), p.589-595

2007

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Power Reduction during Scan Testing Based on Multiple Capture Technique

IEICE transactions on electronics, 2008, Vol.E91-C (5), p.798-805

2008

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Comments on "Filling algorithms and analyses for layout density control"

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-10, Vol.21 (10), p.1209-1211

Lin, Rung-Bin

2002

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Practical ILP-based routing of standard cells

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.245-248

2016

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A Multi-dimensional Pattern Run-Length Method for Test Data Compression

2009 Asian Test Symposium, 2009, p.325-330

2009

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Router and cell library co-development for improving redundant via insertion at pins

2008 IEEE International Conference on Computer Design, 2008, p.646-651

2008

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Variable-sized object packing and its applications to instruction cache design

Computers & electrical engineering, 2008-09, Vol.34 (5), p.438-444

Lin, Rung-Bin

2008

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Simultaneous transistor pairing and placement for CMOS standard cells

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.1647-1652

2015

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Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing

2009 Asian Test Symposium, 2009, p.111-116

2009

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An Internal Pattern Run-Length Methodology for Slice Encoding

ETRI journal, 2011-06, Vol.33 (3), p.374-381

2011

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Conjugate conflict continuation graphs for multi-layer constrained via minimization

Information sciences, 2007-06, Vol.177 (12), p.2436-2447

2007

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Designing and Benchmarking of Double-Row Height Standard Cells

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018, p.64-69

2018

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Reduction of test data volume and test application time by scan chain disabling technique

Journal of the Chinese Institute of Engineers, 2012-09, Vol.35 (6), p.687-696

2012

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Slack budgeting and slack to length converting for multi-bit flip-flop merging

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1837-1842

2013

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Mismatch address indexing for test data compression

Journal of the Chinese Institute of Engineers, 2011-12, Vol.34 (8), p.1035-1045

2011

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Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding

2^ Pattern Run-Length for Test Data Compression

Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

An Internal Pattern Run‐Length Methodology for Slice Encoding

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction

Improving Pin Accessibility of Standard Cells under Power/Ground Stripes

Routing Intent Aware Pin Access Point Selection for Standard Cell Designs

Theoretical analysis of bus-invert coding

Reduction of power dissipation during scan testing by test vector ordering

Reticle Design for Minimizing Multiproject Wafer Production Cost

Power Reduction during Scan Testing Based on Multiple Capture Technique

Comments on "Filling algorithms and analyses for layout density control"

Practical ILP-based routing of standard cells

A Multi-dimensional Pattern Run-Length Method for Test Data Compression

Router and cell library co-development for improving redundant via insertion at pins

Variable-sized object packing and its applications to instruction cache design

Simultaneous transistor pairing and placement for CMOS standard cells

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing

An Internal Pattern Run-Length Methodology for Slice Encoding

Conjugate conflict continuation graphs for multi-layer constrained via minimization

Designing and Benchmarking of Double-Row Height Standard Cells

Reduction of test data volume and test application time by scan chain disabling technique

Slack budgeting and slack to length converting for multi-bit flip-flop merging

Mismatch address indexing for test data compression

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